Posts for si-list, 09-2003

Browse: Last Month: 08-2003 Main Archive Page Next Month: 10-2003

» [SI-LIST] Re: Hspice net? -
» [SI-LIST] Re: [IBIS] Webinar on Differential IBIS Models -
» [SI-LIST] Webinar on Differential IBIS Models -
» [SI-LIST] Re: Split power Plane support for Hyperlynx -
» [SI-LIST] Re: Hspice net? -
» [SI-LIST] Re: Hspice net? -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Fwd: Comments, good bye to wrinkles--- (from Nita Ho) -
» [SI-LIST] Fwd: Comments, good bye to wrinkles--- (from Nita Ho) -
» [SI-LIST] Re: Hardware Design guru - FYI -
» [SI-LIST] Hspice net? -
» [SI-LIST] Anyone doing 802.3ab 1000BT gigabit ethernet SI testing? -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Simulating Wiring Harnesses and Cables. -
» [SI-LIST] Re: Books on Package Design. -
» [SI-LIST] Re: HyperLynx vs Hspice -
» [SI-LIST] Hardware Design guru - FYI -
» [SI-LIST] Re: RJ45 interfacing with RS232 -
» [SI-LIST] Books on Package Design. -
» [SI-LIST] Terminal Emulator supporting 406.8 kbps -
» [SI-LIST] rf measurements -
» [SI-LIST] Split power Plane support for Hyperlynx -
» [SI-LIST] Re: RJ45 interfacing with RS232 -
» [SI-LIST] RJ45 interfacing with RS232 -
» [SI-LIST] power consuming of OSC -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] USB 2.0 testing -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Re: HyperLynx vs Hspice -
» [SI-LIST] FW: eye diagram -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Re: eye diagram -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] (no subject) -
» [SI-LIST] Hspice Toolbox for Matlab -
» [SI-LIST] Re: usage of [Model Spec] Keyword -
» [SI-LIST] Clock phase Margin -
» [SI-LIST] Re: Guard traces for differential pairs -
» [SI-LIST] Re: eye diagram -
» [SI-LIST] Re: HyperLynx vs Hspice -
» [SI-LIST] Signal Integrity-Simplified, new book -
» [SI-LIST] Regarding DFM -
» [SI-LIST] eye diagram -
» [SI-LIST] HSPICE - Deciding Max. route length -
» [SI-LIST] Re: Guard traces for differetial pairs -
» [SI-LIST] Re: Guard traces for differetial pairs -
» [SI-LIST] =?big5?q?=A6^=ABH=A1G?= Re: Guard traces for differetialpairs -
» [SI-LIST] Re: Guard traces for differetial pairs -
» [SI-LIST] usage of [Model Spec] Keyword -
» [SI-LIST] Re: Guard traces for differetial pairs -
» [SI-LIST] Re: HyperLynx vs Hspice -
» [SI-LIST] Re: HyperLynx vs Hspice -
» [SI-LIST] Re: Guard traces for differetial pairs -
» [SI-LIST] Re: Hyperlynx vs. Hspice -
» [SI-LIST] Re: Hyperlynx vs. Hspice -
» [SI-LIST] Re: Hyperlynx vs. Hspice -
» [SI-LIST] Re: Hyperlynx vs. Hspice -
» [SI-LIST] Re: Hyperlynx vs. Hspice -
» [SI-LIST] Re: Hyperlynx vs. Hspice -
» [SI-LIST] Re: Impact of gap on stripline trace -
» [SI-LIST] Re: Impact of gap on stripline trace -
» [SI-LIST] HyperLynx vs Hspice -
» [SI-LIST] HyperLynx vs Hspice -
» [SI-LIST] Re: High Impedance Traces are prone to Radio Frequency Interference -
» [SI-LIST] High Impedance Traces are prone to Radio Frequency Interference -
» [SI-LIST] Guard traces for differetial pairs -
» [SI-LIST] Fr 4 Er variation -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: HSPICE trainings -
» [SI-LIST] HSPICE trainings -
» [SI-LIST] UltraCAD's upgraded freeware transmission line impedance calculator -
» [SI-LIST] Re: Impact of gap on stripline trace -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: Voids in Solder Joints -
» [SI-LIST] Re: TEM Approximation -
» [SI-LIST] lvds TL -
» [SI-LIST] Re: differential pairs crosstalk effect -
» [SI-LIST] Re: differential pairs crosstalk effect -
» [SI-LIST] differential pairs crosstalk effect -
» [SI-LIST] Re: TEM Approximation -
» [SI-LIST] Re: de-embedding of mems -
» [SI-LIST] trade-off between using vias and longer trace length -
» [SI-LIST] Re: Voids in Solder Joints -
» [SI-LIST] Re: Impact of gap on stripline trace -
» [SI-LIST] Re: Impact of gap on stripline trace -
» [SI-LIST] Voids in Solder Joints -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: Impact of gap on stripline trace -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Re: (no subject) -
» (no subject) -
» [SI-LIST] Re: de-embedding of mems -
» [SI-LIST] Re: TEM Approximation -
» [SI-LIST] trade-off between using vias and longer trace length -
» [SI-LIST] Loss Tangent (HELP!) -
» [SI-LIST] Re: TEM Approximation -
» [SI-LIST] Re: Re : maybe something wrong in ebd defination? -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] Re: de-embedding of mems -
» [SI-LIST] high speed connector -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] Re: de-embedding of mems -
» [SI-LIST] de-embedding of mems -
» [SI-LIST] Re: Decoupling capacitor and oscillations -
» [SI-LIST] Re: Antennas (contd) -
» [SI-LIST] Re: SYSTEM CONFIG REQD -
» [SI-LIST] Re: [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition] -
» [SI-LIST] Bus Routing -
» [SI-LIST] Decoupling capacitor and oscillations -
» [SI-LIST] Re: Re : maybe something wrong in ebd definition? -
» [SI-LIST] Re: [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition] -
» [SI-LIST] [Fwd: [IBIS-Users] static/dynamic overshoot/undershoot definition] -
» [SI-LIST] Re: Re : maybe something wrong in ebd definition? -
» [SI-LIST] Re: Re : maybe something wrong in ebd defination? -
» [SI-LIST] Re: Re : maybe something wrong in ebd definition? -
» [SI-LIST] Re: a problem about PLL bypass -
» [SI-LIST] Re: Impact of gap on stripline trace -
» [SI-LIST] SYSTEM CONFIG REQD -
» [SI-LIST] Re: a problem about PLL bypass -
» [SI-LIST] Re : maybe something wrong in ebd defination? -
» [SI-LIST] File access on Yahoo Groups denied -
» [SI-LIST] Re: simulating AC coupling with HSPICE -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] PWL generator for SPICE upgraded -
» [SI-LIST] Re: simulating AC coupling with HSPICE -
» [SI-LIST] Impact of gap on stripline trace -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] Re: simulating AC coupling with HSPICE -
» [SI-LIST] Re: simulating AC coupling with HSPICE -
» [SI-LIST] Re: LVDS cable -
» [SI-LIST] simulating AC coupling with HSPICE -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] Re: LVDS cable -
» [SI-LIST] LVDS cable -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] maybe some oversight in ebd defination? -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] Article on Bounce -
» [SI-LIST] Electrical Specifications for OC-12 -
» [SI-LIST] Re: Manuals for Fastcap and FastHenry -
» [SI-LIST] Decoupling model -
» [SI-LIST] Re: Manuals for Fastcap and FastHenry -
» [SI-LIST] Fabricating an PCB with an odd layer count -
» [SI-LIST] CPCI backplane diode termination -
» [SI-LIST] Manuals for Fastcap and FastHenry -
» [SI-LIST] Re: TEM approximation -
» [SI-LIST] how to improve bus speed in board -
» [SI-LIST] SGMII material -
» [SI-LIST] Invitation to HYTEK & Future Electronics 'Future Faire', a program By Engineers For Engineers (BEFE) -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] AGTL+ transceiver? -
» [SI-LIST] Re: split plane -
» [SI-LIST] Re: impedance relation with frequency... -
» [SI-LIST] Dell Servers Signal Integrity Group has an immediateopening.... -
» [SI-LIST] Signal Integrity opportunity-Austin Texas -
» [SI-LIST] Re: SDRAM connection -
» [SI-LIST] Re: split plane -
» [SI-LIST] impedance relation with frequency... -
» [SI-LIST] split plane -
» [SI-LIST] Re: DDR SDRAM layout considerations -
» [SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) -
» [SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) -
» [SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) -
» [SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) -
» [SI-LIST] Re: Thermal resistance values -
» [SI-LIST] Re: Thermal resistance values -
» [SI-LIST] Re: Thermal resistance values -
» [SI-LIST] Thermal resistance values -
» [SI-LIST] Re: 6 Layer Stack-up (TANSTAAFL) -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: DDR SDRAM layout considerations -
» [SI-LIST] Re: 1394 differential traces -
» [SI-LIST] Re: lumped vs distributed -
» [SI-LIST] Re: simulate isfet model using Hspice -
» [SI-LIST] Re: DDR SDRAM layout considerations -
» [SI-LIST] Job search. -
» [SI-LIST] Re: DDR SDRAM layout considerations -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: RMS Phase Error and BER -
» [SI-LIST] Re: DDR SDRAM layout considerations -
» [SI-LIST] RMS Phase Error and BER -
» [SI-LIST] Thanks for your responses - Re: Re: Antennas (contd) -
» [SI-LIST] Re: 1394 differential traces -
» [SI-LIST] Re: lumped vs distributed -
» [SI-LIST] DDR SDRAM layout considerations -
» [SI-LIST] Re: Interfacing DDR 400 DRAM Chips to Xilinx Virtex II FPGA. -
» [SI-LIST] Interfacing DDR 400 DRAM Chips to Xilinx Virtex II FPGA. -
» [SI-LIST] peeling algorithm -
» [SI-LIST] help in mentorgraphics librarian -
» [SI-LIST] 1394 differential traces -
» [SI-LIST] simulate isfet model using Hspice -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] lumped vs distributed -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Non-negative off diagonal capacitive matrix -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Call for participation deadline extended -
» [SI-LIST] Re: Antennas (contd) -
» [SI-LIST] Re: Antennas (contd) -
» [SI-LIST] Length matching of differential pair -
» [SI-LIST] Re: SDRAM connection -
» [SI-LIST] Re: SDRAM connection -
» [SI-LIST] Change in access to si-list files on Yahoogroups site -
» [SI-LIST] SDRAM connection -
» [SI-LIST] Re: A question about data mask in SDRAM/DDR -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] sorry to bother,dont mind my former mail "how can I use the R params in EBD file path Description?" -
» [SI-LIST] how can I use the R params in EBD file path Description? -
» [SI-LIST] RMCEMC August Presentation Download available -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] Re: 6 Layer Stack-up -
» [SI-LIST] 6 Layer Stack-up -
» [SI-LIST] Re: Diff. Bal. to Unbal. Transition -
» [SI-LIST] Re: Diff. Bal. to Unbal. Transition -
» [SI-LIST] Antennas (contd) -
» [SI-LIST] Re: Diff. Bal. to Unbal. Transition -
» [SI-LIST] Re: regarding 1394 firewire -
» [SI-LIST] Re: GND is perfect conductor? -
» [SI-LIST] Re: Diff. Bal. to Unbal. Transition -
» [SI-LIST] regarding 1394 firewire -
» [SI-LIST] Re: GND is perfect conductor? -
» [SI-LIST] Re: Antenna's -
» [SI-LIST] Significant error in signal measurements -
» [SI-LIST] RMCEMC Aug Meeting downloads and other offerings -
» [SI-LIST] RMCEMC September Meeting Announcement -
» [SI-LIST] Re: Antenna's -
» [SI-LIST] Re: Where Can I Get FastHenry and FastCap -
» [SI-LIST] Re: Where Can I Get FastHenry and FastCap -
» [SI-LIST] Where Can I Get FastHenry and FastCap -
» [SI-LIST] Diff. Bal. to Unbal. Transition -
» [SI-LIST] Antenna's -
» [SI-LIST] Re: si-list Digest V3 #259 -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] Re: Reference Plane -
» [SI-LIST] Re: Return Path Usage -
» [SI-LIST] Return Path Usage -
» [SI-LIST] Re: Reference Plane -
» [SI-LIST] Re: Reference Plane -
» [SI-LIST] GND is perfect conductor? -
» [SI-LIST] Re: Reference Plane -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] Re: Reference Plane -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] Reference Plane -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] Re: Is this kind of software available in the market? -
» [SI-LIST] AW: FastHenry .external and .equiv -
» [SI-LIST] TEM approximation -
» [SI-LIST] trying to get in touch with the listed people -
» [SI-LIST] Re: GND is perfect conductor? -
» [SI-LIST] Re: (EMI)spread spectrum clocking -
» [SI-LIST] Re: Fwd: Re: relation b/w impedance and SI -
» [SI-LIST] transmission line characteristic impedance (Zo) value -
» [SI-LIST] Re: Inductance of wire section -
» [SI-LIST] Impact of finite and irregular ground planes on stripline bandwidth -
» [SI-LIST] Re: (EMI)spread spectrum clocking -
» [SI-LIST] Re: (EMI)spread spectrum clocking -
» [SI-LIST] =?big5?q?=A6^=ABH=A1G?= Is this kind of softwareavailable in the market? -
» [SI-LIST] Re: (EMI)spread spectrum clocking -
» [SI-LIST] Re: (EMI)spread spectrum clocking -
» [SI-LIST] FastHenry .external and .equiv -
» [SI-LIST] Is this kind of software available in the market? -
» [SI-LIST] Re: Inductance of wire section -
» [SI-LIST] Re: Inductance of wire section -
» [SI-LIST] Re: Inductance of wire section -
» [SI-LIST] Parasitic resonance in DC-DC converters -
» [SI-LIST] Re: Inductance of wire section -
» [SI-LIST] Re: FW: Inductance of wire section -
» [SI-LIST] Re: GMII & RGMII timing analysis -
» [SI-LIST] Re: (EMI)spread spectrum clocking -
» [SI-LIST] Re: FW: Inductance of wire section -
» [SI-LIST] (EMI)spread spectrum clocking -
» [SI-LIST] Fwd: Re: relation b/w impedance and SI -
» [SI-LIST] Re: Inductance of wire section -
» [SI-LIST] Re: FW: Inductance of wire section -
» [SI-LIST] Re: GND is perfect conductor? -
» [SI-LIST] Re: FW: Inductance of wire section -
» [SI-LIST] Re: Job Opportunities -
» [SI-LIST] FW: Inductance of wire section -
» [SI-LIST] Inductance of wire section -
» [SI-LIST] Re: GND is perfect conductor? -
» [SI-LIST] Re: GND is perfect conductor? -
» [SI-LIST] GND is perfect conductor? -
» [SI-LIST] IEEE CPMT Society Phoenix Chapter - 9/22/03 meeting announcement -
» [SI-LIST] Re: testing LVPECL signal with 50ohm system -
» [SI-LIST] Interface for FLat panel Displays -
» [SI-LIST] Re: HSpice implementation of recursive convolution -
» [SI-LIST] relation b/w impedance and SI -
» [SI-LIST] Re: HSpice implementation of recursive convolution -
» [SI-LIST] Re: HSpice implementation of recursive convolution -
» [SI-LIST] Re: RF ground in RF chip -
» [SI-LIST] Re: testing LVPECL signal with 50ohm system -
» [SI-LIST] Re: HSpice implementation of recursive convolution -
» [SI-LIST] Re: RF ground in RF chip -
» [SI-LIST] Re: HSpice implementation of recursive convolution -
» [SI-LIST] testing LVPECL signal with 50ohm system -
» [SI-LIST] ground in RF chip -
» [SI-LIST] Re: Model of Capacitors -
» [SI-LIST] Re: RF ground in RF chip -
» [SI-LIST] HSpice implementation of recursive convolution -
» [SI-LIST] HSpice recursive convolution implementation -
» [SI-LIST] Re: Model of Capacitors -
» [SI-LIST] Re: Model of Capacitors -
» [SI-LIST] Re: Model of Capacitors -
» [SI-LIST] RF ground in RF chip -