Hi All, I would appreciate recommendations on layout for series DC block capacitors, so as to minimize the impedance mismatch. The signal is 2.5Gb/s, 100 ohms differential, with nominal 80ps rise and fall times and is fairly short - only a few centimetres. I would prefer to use 0402 size caps. Do the caps have to be special RF type or can standard X7R or NPO caps be used? In addition, I would like to use the point where the series caps are connected for a dual layout option - top layer to one device and bottom layer to an alternative device. Is this a risky choice ? I've seen it on an eval board from our device vendor, but I'd like some insight from the experts. Also does anyone have some guidance on interfacing to coaxial optical packages, such as ROSA/TOSA/TO45 CAN. Our application requires mounting parallel to the board, but the packages are through hole, vertical mount. I suspect that the interfacing to the leads is not straightforward to get a decent impedance match. I thought that it may be possible to mount on the edge of the board, with leads soldered above and below. Thanks, Bernard Harris Lynx Photonic Networks ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List FAQ wiki page is located at: http://si-list.org/wiki/wiki.pl?Si-List_FAQ List technical documents are available at: http://www.si-list.org List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu