[SI-LIST] Re: Question about package models
- From: "Zabinski, Patrick J." <zabinski.patrick@xxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 19 Jul 2001 14:40:55 -0500
> Hi guys:
> A couple of questions about the use of package models.
>
> 1) Do any of you use device package models when designing high-speed
> boards?
Absolutely. Depending upon the package, speed, technology,
etc., the package can completely destroy the signal, and
it's best to know/understand this and find work-arounds
*before* the board is built.
> 2) If so, what model is preferred, spice/RLC, S-parameter, other?
Most of the time, we don't have much choice. IBIS provides
simple lumped LRC, while some RF vendors supply S-parameters.
If I have choice, I prefer a spice model that includes
T-lines for "long" (as defined by the edge rate) traces/leads
and lumped LRC for bond wires, vias, "short" leads, etc.
> 3) If the package is controlled impedance and the device has on-chip
> termination, would you still have a use for the package model?
Again, yes. In most cases I've seen, if the vendor has
gone through the effort/expense of controlled impedance package
and on-chip termination, you're *likely* safe without
simulation, but it's still worth the effort verification
through simulation.
>
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
