[SI-LIST] Question about package models
- From: Allan Davidson <allan.davidson@xxxxxxxxxxxxxxx>
- To: "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 19 Jul 2001 12:26:01 -0700
Hi guys:
A couple of questions about the use of package models.
1) Do any of you use device package models when designing high-speed
boards?
2) If so, what model is preferred, spice/RLC, S-parameter, other?
3) If the package is controlled impedance and the device has on-chip
termination, would you still have a use for the package model?
Thanks in advance.
Regards, Allan
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