[SI-LIST] Re: QDR <=> Processor interface
- From: Dagmara Avanindra <dagmara.avanindra@xxxxxxxxx>
- To: igazula@xxxxxxxxxxx
- Date: Wed, 20 Jul 2005 13:48:43 -0700
Indira,=20
since you're using K &/K for writing and C & /C for Reading, you
should be more concerned with matching data and clocks rather then
absolute length.
I have not seen max length requirements from vendors from QDR
myself; maybe it was just a length they did on the reference board?
I don't think it would hurt for you to exceed 3" a bit as long as
you don't switch reference layers too much and keep xtalk down.
Dagmara
On 7/20/05, Indira Gazula <igazula@xxxxxxxxxxx> wrote:
> Hi Dagmara,
>=20
> Thanks for the feedback. What I forgot to mention earlier is that it is s=
ource sync interface and is meeting the timing constraints (set-up and hold=
margins)even for longer lengths. There is no particular limit on propogati=
on delay. Considering this, what would you say is limiting the length?
>=20
> Indira.
> Dagmara Avanindra <dagmara.avanindra@xxxxxxxxx> wrote:
> Indira,
>=20
> when deceiding upon the trace length, it is important to remember not
> just the quality of the signal (clean rise time, voltage margin) but
> also timing constraints. You need to take into account propogation
> delay into your timing margin. Look at the timing spec of the
> interface, and perhaps that will make more sense on length constraint.
>=20
> The shunt resistor is there to kill off reflections, for having
> reflections can break a tight timing interface. You can get rid of the
> resistors in your simulation, and see the difference. If your
> microprocessor has well-controlled output impedance, there may be a
> chance that you can get away without the termination resistors. But
> you need to do simulations to confirm that.
>=20
> Thanks,
> Dagmara
>=20
>=20
>=20
> On 7/20/05, Indira Gazula wrote:
> > Hi All,
> >
> > I have recently stepped into the world of SI and would appreciate any i=
nputs on my question:
> >
> > I am working on the interface between a QDR-II SRAM and Processor (163 =
Hz clock, 1.5V). The suggestions for this interface is that trace length sh=
ould not exceed ~3000mil. This particular interface has a shunt resistor of=
50Ohm to 0.75V on the QDR side. Simulations suggest longer trace lengths g=
ive acceptable performance for much longer trace lengths. Could anyone plea=
se explain why it is suggested that trace lenght should be restricted to 3i=
n, also how it would be different if there is no shunt termination (is it r=
equired).
> >
> > Thanks in advance for the help.
> >
> > Best Regards,
> >
> > Indira.
> >
> >
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>=20
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