Posts for si-list, 07-2005

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» [SI-LIST] Re: ååï Re: differential signaling (common-mode) -
» [SI-LIST] Re: 回复： Re: [SI-LIST] differential signal in g (common-mode) -
» [SI-LIST] 回复： Re: differential signaling (common-mode) -
» [SI-LIST] Re: 回复： Re: [SI-LIST] differential signal in g (common-mode) -
» [SI-LIST] 回复： Re: differential signaling (common-mode) -
» [SI-LIST] Re: differential signaling (common-mode) -
» [SI-LIST] differential signaling (common-mode) -
» [SI-LIST] Re: ??: Re: How to use Intel's model? -
» [SI-LIST] Re: ??: Re: How to use Intel's model? -
» [SI-LIST] Re: ibis models needed -
» [SI-LIST] Re: ibis models needed -
» [SI-LIST] Re: ibis models needed -
» [SI-LIST] ibis models needed -
» [SI-LIST] 回复： Re: How to use Intel's model? -
» [SI-LIST] 回复： Re: How to use Intel's model? -
» [SI-LIST] Re: HSPICE to IBIS -
» [SI-LIST] Re: HSPICE to IBIS -
» [SI-LIST] Re: How to use Intel's model? -
» [SI-LIST] Re: HSPICE to IBIS -
» [SI-LIST] Re: HSPICE to IBIS -
» [SI-LIST] Re: HSPICE to IBIS -
» [SI-LIST] Re: [SI-LIST]network analysis of differential signal using hspice -
» [SI-LIST] Re: [SI-LIST]network analysis of differential signal using hspice -
» [SI-LIST] Re: LVTTL SSTL interface -
» [SI-LIST] [SI-LIST]network analysis of differential signal using hspice -
» [SI-LIST] HSPICE to IBIS -
» [SI-LIST] Re: LVTTL SSTL interface -
» [SI-LIST] Re: EMPIRE Software Package Experiences? -
» [SI-LIST] LVTTL SSTL interface -
» [SI-LIST] How to use Intel's model? -
» [SI-LIST] Re: [IBIS-Users] IBIS Question -
» [SI-LIST] EMPIRE Software Package Experiences? -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDRII OCD and ODT -
» [SI-LIST] DDRII OCD and ODT -
» [SI-LIST] Differential signal transmission using microstrip cable -
» [SI-LIST] subscribe -
» [SI-LIST] 2006 EMC Symposium in Singapore -
» [SI-LIST] solicting articles for Handheld Tester application note -
» [SI-LIST] High speed connector design -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] DDR Vref Bypassing - Please explain pseudo diff -
» [SI-LIST] Re: four S channels VNA -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: four S channels VNA -
» [SI-LIST] Re: QDR <=> Processor interface -
» [SI-LIST] Re: four S channels VNA -
» [SI-LIST] Re: four S channels VNA -
» [SI-LIST] Ailtech mauals -
» [SI-LIST] four S channels VNA -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: QDR <=> Processor interface -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: QDR <=> Processor interface -
» [SI-LIST] Re: QDR <=> Processor interface -
» [SI-LIST] QDR <=> Processor interface -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: FIR Filter Design -
» [SI-LIST] Re: FIR Filter Design -
» [SI-LIST] FIR Filter Design -
» [SI-LIST] Re: via model -
» [SI-LIST] Re: SPAM: Score 3.9: Re: HSPICE and Via Modeling -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: Electrostatic HiZ PCBs -
» [SI-LIST] Re: Electrostatic HiZ PCBs -
» [SI-LIST] Re: Field EM Meter -
» [SI-LIST] Re: Jitter in the output of PLL -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: Electrostatic HiZ PCBs -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: HSPICE and Via Modeling -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: HSPICE and Via Modeling -
» [SI-LIST] Re: HSPICE and Via Modeling -
» [SI-LIST] Re: HSPICE and Via Modeling -
» [SI-LIST] Re: HSPICE and Via Modeling -
» [SI-LIST] Re: HSPICE and Via Modeling -
» [SI-LIST] Re: HSPICE and Via Modeling -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Re: Field EM Meter -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Field EM Meter -
» [SI-LIST] HSPICE and Via Modeling -
» [SI-LIST] Re: DDR Vref Bypassing -
» [SI-LIST] Electrostatic HiZ PCBs -
» [SI-LIST] DDR Vref Bypassing -
» [SI-LIST] Mixed Mode S-Parameters and Touchstone Format Files -
» [SI-LIST] Intel looking for experienced Signal Integrity engineer -
» [SI-LIST] SPAM on si-list -
» [SI-LIST] Jitter in the output of PLL -
» [SI-LIST] Make Your Website More Profitable -
» [SI-LIST] Perl scripts for reformatting Touchstone to simple xy table -
» [SI-LIST] mvt -
» [SI-LIST] Re: Regarding the air gap between via hole and copper -
» [SI-LIST] Re: Regarding the air gap between via hole and copper -
» [SI-LIST] Re: Regarding the air gap between via hole and copper -
» [SI-LIST] Re: Regarding the air gap between via hole and copper -
» [SI-LIST] Re: R: About XTK layout file transfer issue -
» [SI-LIST] Re: IBIS about differential output -
» [SI-LIST] Re: R: About XTK layout file transfer issue -
» [SI-LIST] R: About XTK layout file transfer issue -
» [SI-LIST] Is there fiberglass in ROGERS material ? -
» [SI-LIST] Regarding the air gap between via hole and copper -
» [SI-LIST] IBIS about differential output -
» [SI-LIST] About XTK layout file transfer issue -
» [SI-LIST] Re: 4 Ghz PCB -
» [SI-LIST] Re: 4 Ghz PCB -
» [SI-LIST] 4 Ghz PCB -
» [SI-LIST] Re: SI Consultants? -
» [SI-LIST] Re: SI Consultants? -
» [SI-LIST] Re: Signal Integrity training -
» [SI-LIST] SI Consultants? -
» [SI-LIST] Re: R: Too much predicted loss -
» [SI-LIST] R: R: Too much predicted loss -
» [SI-LIST] Re: Too much predicted loss -
» [SI-LIST] Re: Too much predicted loss -
» [SI-LIST] Re: Too much predicted loss -
» [SI-LIST] Re: R: Too much predicted loss -
» [SI-LIST] DDR-1 termination -
» [SI-LIST] Re: R: Too much predicted loss -
» [SI-LIST] Re: R: Too much predicted loss -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: si-list Digest V5 #275 -
» [SI-LIST] unsubscribe -
» [SI-LIST] Re: si-list Digest V5 #275 -
» [SI-LIST] R: Too much predicted loss -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: Too much predicted loss -
» [SI-LIST] Too much predicted loss -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Re: Resistors to use for DDR termination -
» [SI-LIST] Resistors to use for DDR termination -
» [SI-LIST] Re: R: Re: Impedance deviation due to prepreg shrinking -
» [SI-LIST] Re: R: Re: Impedance deviation due to prepreg shrinking -
» [SI-LIST] R: Re: Impedance deviation due to prepreg shrinking -
» [SI-LIST] Re: EBD in HSPICE -
» [SI-LIST] Re: Impedance deviation due to prepreg shrinking -
» [SI-LIST] Impedance deviation due to prepreg shrinking -
» [SI-LIST] How to create connector's IBIS model from S-Parameters? -
» [SI-LIST] How to check Capacitance in IBIS model -
» [SI-LIST] EBD in HSPICE -
» [SI-LIST] Signal Integrity training -
» [SI-LIST] scope errors by emi from signal source -
» [SI-LIST] Re: The effect of temperature on the speed of IC -
» [SI-LIST] Re: The effect of temperature on the speed of IC -
» [SI-LIST] Re: SEU caused by laser illumination -
» [SI-LIST] Re: The effect of temperature on the speed of IC -
» [SI-LIST] Re: The effect of temperature on the speed of IC -
» [SI-LIST] Re: Balancing Copper and dielectric losses? -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: Balancing Copper and dielectric losses? -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Balancing Copper and dielectric losses? -
» [SI-LIST] Re: power layer question -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: Modeling Connectors and Relays -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] power layer question -
» [SI-LIST] Re: Chip input capacitance -
» [SI-LIST] AWR SI tools -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: Chip input capacitance -
» [SI-LIST] Chip input capacitance -
» [SI-LIST] Re: The effect of temperature on the speed of IC -
» [SI-LIST] Re: The effect of temperature on the speed of IC -
» [SI-LIST] The effect of temperature on the speed of IC -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: SEU caused by laser illumination -
» [SI-LIST] Modeling Connectors and Relays -
» [SI-LIST] Re: Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Q on Trace Width and Jitter for Diff Pairs -
» [SI-LIST] Re: stitching vias -
» [SI-LIST] Paper: Eye Diagrams and BERT for Digital System Interconnect Analysis -
» [SI-LIST] Re: stitching vias -
» [SI-LIST] Re: stitching vias -
» [SI-LIST] SI/Packaging Posting -
» [SI-LIST] stitching vias -
» [SI-LIST] Re: problems with simulation of loop antenna far field using Wire-MOM -
» [SI-LIST] Re: SEU caused by laser illumination -
» [SI-LIST] Isolating feeder cable parasitics in Eye diagram measurement -
» [SI-LIST] problems with simulation of loop antenna far field using Wire-MOM -
» [SI-LIST] SEU caused by laser illumination -
» [SI-LIST] New Packaging SI Opportunity ... -
» [SI-LIST] Agilent TDR Normalization Questions -