[SI-LIST] Re: Power Supply Distribution/Filtering/Decouplin g Guide]
- From: steve weir <weirsp@xxxxxxxxxx>
- To: vrbanacm@xxxxxxxxxx, swldstn@xxxxxxxxxxxx,
- Date: Wed, 14 Jan 2004 00:11:25 -0800
Michael,
Thanks. I absolutely agree that we need to approach this in a way that is
practical and effective for both the chip vendors and their customers.
I don't look at this as a digital or analog problem. I view it as a
frequency response problem. In my funny way of thinking, what I think we
need is analogous to a reference impedance.
I view the reference constructions as a way of providing just that. They
are nothing more than reference impedances, where the specific impedance to
structures inside a given component is defined by a series of physical
structures that are the combination of the reference constructions, and the
interconnect that is component specific. It is if you will an extension
of the IBIS turned somewhat inside-out.
I admit that by limiting the reference structures to a hopefully small set,
we impose burden on chip suppliers that they may not initially be very
happy with. Ie:
1. Effort to constrain their designs to function properly with at least one
of the reference constructions, and
2. Exposure to criticism for chips that impose expensive and/or very
difficult system requirements.
Being on the system side, and powerless to do anything more than apply
band-aids to hemorrhaging chips, my conviction is that many chip vendors
have long been remiss in their responsibilities. It is agony to either
work in the dark, and/or spin boards to fix problems that proper analysis
could easily have avoided if only we had decent data in the first place.
In exchange for the pain this imposes on chip vendors, the industry should see
1. Higher first time system yields.
2. Accelerated design cycles, ( results from 1. )
3. Lower system costs, PWB and PDS overdesign reduction.
4. Lower development costs by elimination of prototype / test / reprototype.
5. Better visibility on both sides to true system cost.
We all know the mantra of profits translating directly from time to
market. All of the above accelerates time to market, profits to system
vendors, which means more profit opportunity to the chip houses. Let's get
this ugly source of errors that forces expensive and time-consuming tooling
spins out of our development cycle.
Once we can agree on reference constructions to work from, we can apply an
arbitrary amount of analysis on either side of the fence. This makes a
whole lot more sense to me than chip by chip reference designs that meet
specific needs of a device vendor to demonstrate their chip, but usually
fail to adequately parameterize what the chip really needs from the PWB / PDS.
The only difference between a digital and analog circuit at that point are
the coefficients in an impedance profile versus frequency, and current
profile versus time.
Regards,
Steve.
At 01:25 AM 1/14/2004 -0600, Michael E. Vrbanac wrote:
>Steve,
>
>Your points are quite important and represent the other half of the problem.
>In my opinion, the best thing would be to have the best minds on both sides of
>the issue working on making this happen in a win-win situation. Assuming
>that component performance is going to advance, its no mystery that eventually
>power decoupling is going to end up in the package and die. So it seems
>inevitable regardless of what we think the cost is now. Besides, cost
>seems to
>plummet after folks have expended a good deal of effort to solve the
>problem and
>find a good way to do it. The only thing left to decide is whether we'll
>let the problem
>kick us in the seat of the pants or whether we look at this thing squarely
>and handle
>it now.
>
>The industry has done things like this many times before and the cost was
>staggering
>initially but everyone survived. We'll make it through this one,
>too. There's just too many
>bright folks interested in this one. I hope you'll be one of the folks
>that will be able
>to make it happen.
>
>Finally, in looking at how to communicate to engineers regarding decoupling
>requirements for your products, how would you tell them to do their decoupling
>for a variety of design situations since not all folks are doing "digital
>only" designs
>and some have special low power noise requirements? Since they know their
>specific design requirements and you probably wouldn't, how might we help them
>know "when" to beef up or reduce the decoupling design complexity?
>
>Best Regards,
>
>Michael E. Vrbanac
>
>
>At 11:03 PM 1/13/2004 -0500, Steven M. Waldstein wrote:
> >To all,
> >
> >As a component designer we also struggle with the best trade-offs
> >of power delivery and how they impact component cost. Often times
> >we are forced to find the lowest cost solution that is sub optimum
> >because we continually pressured on price. Eliminating on package
> >capacitor saves money as well as smaller die with less on die
> >decoupling.
> >
> >An other example of this is package size. I think larger, easier
> >to route ( in the package and on the board ) are a better trade off
> >but customers push on cost the forces us into smaller BGA substrates
> >that offer poorer signal quality and more PCB layers so the component
> >cost, not system cost, can be optimized.
> >
> >Even with this we have adopted a philosophy that the die/package/PCB
> >power delivery must work and we do reference designs we think are
> >representative of end user systems and technology. That's the best way
> >we know of the deliver a quality product. The faster end users can
> >design and field their systems the sooner we see volume purchases.
> >We want to lower or eliminate the system integrators barriers.
> >
> >Steve
> >swldstn@xxxxxxxxxxxx
>
>
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