[SI-LIST] Re: Power Supply Distribution/Filtering/Decouplin g Guide]
- From: steve weir <weirsp@xxxxxxxxxx>
- To: Chris.Cheng@xxxxxxxxxxxx,"'Larry.Smith@xxxxxxx'" <Larry.Smith@xxxxxxx>, scott@xxxxxxxxxxxxx
- Date: Tue, 13 Jan 2004 17:39:45 -0800
Chris,
I think there is fairly good agreement here that the series combination of
the spreading and interconnect ( via / pad ) inductance is in series with
the package inductance and so both:
1) Shifts the SRF of the power feed to the package internals, and
2) Shifts the impedance seen into the package.
For a .062 board with only 4 or 6 layers, the planes are going to be far
away from the package. The via length is going to be long and the dominant
factor in the inductance. In that case improving the spreading inductance
has diminishing returns.
However for a board with many layers where layers 2 and 3 are available for
planes, and assuming plentiful pwoer / ground connections, thinning the
dielectric can have a pronounced effect on total connected inductance.
The question returns, what has the IC been designed to require?
If an IC is designed to be "well behaved" then IMO there should be enough
internal capacitance, and sufficient quantity of power / ground
interconnect so that when mounted on a benchmark .062, six layer board,
with 14 mil power/ground separation L2 to L5, the resulting inductance
remains within device design margins. Perhaps that should be considered
the "commercial preferred" standard and deserve an approved mark of some
sort.
Devices that for whatever reason cannot tolerate the "standard" plane
attachment can stipulate the external inductance, and / or other special
interconnect that they require. If that demands thin dielectrics and extra
planes close to the surface to meet, then the buyer is forewarned. Just
facing such a stigma, might be enough to shame many companies into doing a
better job with their IC's in order to avoid crucifixtion by their
competitors' marketing dept's. At any rate it would allow quantification
of the cost and effort to use Vendor A versus Vendor B's parts.
If we further had based on that benchmark a current demand profile /
impedance profile, any competent board engineer could then readily design
an appropriate PDS.
Steve.
At 05:03 PM 1/13/2004 -0800, Chris Cheng wrote:
>Larry,
>I would argue the processor socket and not the PCB plane spreading
>inductance will be the dominant inductance that determines the dividing line
>between the PCB and chip/package responsibility.
>It also brings back the original question I raise to Scott, at 1-100MHz at
>the system level, do these spreading inductance matters ? Especially for the
>relatively smaller size chipset packages (as compared to a big processor
>module). Do you think that decoupling cap being placed 1/2 inch from the
>center really needs that extra thin core power/gnd plane pair inductance to
>make a difference ?
>Chris
>
>-----Original Message-----
>From: Larry Smith [mailto:Larry.Smith@xxxxxxx]
>Sent: Tuesday, January 13, 2004 3:02 PM
>To: scott@xxxxxxxxxxxxx
>Cc: silist
>Subject: [SI-LIST] Re: Power Supply Distribution/Filtering/Decouplin g
>Guide]
>A side note - the buried capacitance of the PCB power planes is not
>very important in this frequency range but the spreading inductance
>associated with the dielectric thickness is extremely important. In
>many cases, it is the power plane spreading inductance that dominates
>the the mounting inductance for the chip/package, and therefor
>determines the chip/package resonant frequency (the dividing line
>between PCB and chip/package responsibility for the PDS).
>Perforations in the PCB power planes greatly exacerbate the situation.
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