[SI-LIST] Re: PDN related
- From: Ranganath Narayana <ranganath.narayana@xxxxxxxxx>
- To: Scooby Doo <si.scooby@xxxxxxxxx>
- Date: Mon, 15 Mar 2010 20:46:58 +0530
Hi Scooby,
Selection of Decap should be choosed based on ,
Supply Voltage,Max current sink from supply,Transient
current,VripplePk-Pk,Frequency target
and also VRM properties.
Please refer attached PDN design tool,also available for free in Altera
website
With Regards
Ranga
+91-9632330203
On Mon, Mar 15, 2010 at 8:24 PM, Scooby Doo <si.scooby@xxxxxxxxx> wrote:
> Hi SI Experts,
>
>
> I have a question reg PDN.
>
> Suppose an FPGA has 100 I/O pins with 10 VCCO/Gnd pairs. So an average
> of 10 I/O pins for 1 VCCO/Gnd pair. Assume each I/O pin driving 10pf load.
>
> My qn is, to make the clean PDN, is it enough to provide 100pf of capacitor
> to each Vcc/Gnd pair?
>
> I am not convinced with blindly provinding 0.1uF cap to Vcco pins.
>
> kindly clarify.
>
> Thanks in advance for your valuable feedback.
>
> Rajesh
>
>
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