Lynne and All, One more caveat: the metric to judge the PDN performance is very important. There are applications where the noise power matters more, in those applications widening the PDN bandwidth with Q>1 capacitors works very well. There are other applications, where the worst-case instantaneous noise voltage matters, and in those cases any impedance profile that deviates from a smooth R-L equivalent impedance will result in an increase of noise. Regards, Istvan Novak Oracle steve weir wrote: > Lynne, there has been for many years an incorrect notion that bypass > capacitors are not effective past their mounted SRF. This is at best a > truism. The fact is that bypass capacitors work just fine decades > beyond their mounted SRF. Istvan's DMB/DMI scheme that you will find > detailed on his web site that you've referenced relies on this fact. > > At the beginning and end of the key issue in power delivery is > inductance. If you are concerned with either or both cost and > performance inductance of the components and interconnect is the > limiting factor to both. Inductance drives basic impedance. Inductance > drives Q in resonances. > > INDUCTANCE DRIVES THE NUMBER OF BYPASS CAPACITORS REQUIRED NO MATTER > WHAT APPROACH IS USED FOR CAPACITOR VALUE SELECTION. > > While many pole networks can be very useful and Sigrity's Optimize > PI(tm) customers are generally getting good results with that tool's > approach, beware the rat hole of a many pole FD impedance plot: Those > plots reflect voltage / current relations for circulating currents. > This is Bruce's big caveat and one of the big reasons why he is so > insistent on TD analysis. > > Best Regards, > > > Steve. > > Lynne D. Green wrote: > >> Hi, Steve and Rajesh, >> >> Enough caps of one size will work, until your signal content goes too >> far past the resonance frequency. >> And yes, different packages have different parasitics and different >> resonance freqs. >> >> Using a variety of (carefully selected) caps covers a wider frequency >> range (several decades). >> At the same time, this reduces the total number of caps needed, and >> quite possibly total cost. >> These days, there are EDA tools to make this easier. >> >> And I agree wholeheartedly with Lee that there are plenty of good >> books out there. Istvan Novak's >> home page lists several of them. http://www.electrical-integrity.com/ >> >> Lynne >> >> >> steve weir wrote: >> >>> And yet there are any number of boards and systems that have been >>> built using mostly one capacitor value such as 0.1uF that work fine. >>> >>> Steve. >>> >>> Scooby Doo wrote: >>> >>>> Hi Lynne, >>>> >>>> This is what exactly what is wanted to ask. If the slew rate is >>>> 1v/ns, then my 0.1uF capacitor value (designers blindly using value) >>>> will not support due to existance inductive nature at that frequency. >>>> >>>> >>>> So kindly give some reference / notes so that choosing right value. >>>> >>>> >>>> >>>> >>>> --- On Mon, 3/15/10, Lynne D. Green <lgreen22@xxxxxxxxxxxxxx> wrote: >>>> >>>> >>>> From: Lynne D. Green <lgreen22@xxxxxxxxxxxxxx> >>>> Subject: [SI-LIST] Re: PDN related >>>> To: "Scooby Doo" <si.scooby@xxxxxxxxx> >>>> Cc: "SI LIST" <si-list@xxxxxxxxxxxxx> >>>> Date: Monday, March 15, 2010, 5:20 PM >>>> >>>> >>>> Depends on the frequency range where you need PDN clean. >>>> If it is a wide range (generally true) then one would use >>>> more than one value of capacitor. Remember, capacitor >>>> impedance increases at high frequency due to inductive >>>> package effects. >>>> >>>> Lynne >>>> >>>> >>>> "IBIS training when you need it, where you need it." >>>> >>>> Dr. Lynne Green >>>> Green Streak Programs >>>> http://www.greenstreakprograms.com >>>> 425-788-0412 >>>> lgreen22@xxxxxxxxxxxxxx >>>> >>>> >>>> Scooby Doo wrote: >>>> >>>> >>>>> Hi SI Experts, >>>>> I have a question reg PDN. >>>>> Suppose an FPGA has 100 I/O pins with 10 VCCO/Gnd pairs. So an >>>>> average of 10 I/O pins for 1 VCCO/Gnd pair. Assume each I/O pin >>>>> driving 10pf load. >>>>> My qn is, to make the clean PDN, is it enough to provide 100pf of >>>>> capacitor to each Vcc/Gnd pair? >>>>> I am not convinced with blindly provinding 0.1uF cap to Vcco pins. >>>>> kindly clarify. >>>>> Thanks in advance for your valuable feedback. >>>>> Rajesh >>>>> >>>>> >>>>> >>>> ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu