[SI-LIST] Re: PDN design
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Jennifer Maharani <jennifer.maharani@xxxxxxxxx>
- Date: Wed, 24 Mar 2010 06:48:35 -0700
How long does it take to run a comprehensive transient simulation?
How do you develop the stimulus for your simulation to ensure you catch
the worst case(s)?
Steve.
Jennifer Maharani wrote:
> Hello all,
>
> In designing PDN (chip-pkg-board), many people do frequency domain
> analysis to determine the impedance of the PDN. What is it for? As far
> as power integrity is concerned, isn't it better and enough to run
> transient simulation to see the PWR/GND bounce seen from the chip e.g.
> I/O ?
>
> Many thanks,
> Jenni
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