[SI-LIST] PDN design
- From: Jennifer Maharani <jennifer.maharani@xxxxxxxxx>
- To: si list silist <si-list@xxxxxxxxxxxxx>
- Date: Wed, 24 Mar 2010 14:33:56 +0100
Hello all,
In designing PDN (chip-pkg-board), many people do frequency domain
analysis to determine the impedance of the PDN. What is it for? As far
as power integrity is concerned, isn't it better and enough to run
transient simulation to see the PWR/GND bounce seen from the chip e.g.
I/O ?
Many thanks,
Jenni
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