[SI-LIST] Re: Optimal Power/ground lauout for a 2-layer PCB
- From: Neeraj Pendse <cnepsc@xxxxxxxxxxxxxxx>
- To: AdeelM@xxxxxxxxxxxx
- Date: Sat, 02 Mar 2002 17:26:22 -0800
Adeel,
I suggest you take a look at the following book:
High Speed Digital Design, a Handbook of Black Magic
by Dr. Howard Johnson
I believe that this book contains some strategies on analog and digital
power decoupling. There is another, newer (and presumably better) book
that has been written on this subject - but I do not remember its name
... hopefully someone will recall it.
Regarding the impedence requirement from the power supply subsystem, you
will have to analyze the resistance, inductance and capacitance of the
power and ground loop. Since 50MHz is very slow if your board is less
than 6 inches, then you should be fine. Is 50MHz data/clock frequency or
sinusoidal AC frequency? You will have to approximate the RLC values
based on the placement and lengths. You can either use closed form
equations (found in any electronic design handbook) or field simulators
to do this.
I could not tell you if 0.1-ohm criterion can be met unless I know what
specific layout you have. But at 50MHz, I am guessing it should not be a
problem
Hope this helps,
- Neeraj
> Adeel Malik wrote:
>
> Hi All,
> I have a task to design a 2-layer board with a very packed
> circuitry and so, no luxury of having the ground or power planes. The power
> supplies provided to the board are +5V, -24V and -48V, through a DIN-96
> connector.
> I have two questions:
>
> 1. Digital components would be fed directly from +5V supply whereas I have
> to generate +5V Analog (for Analog ICs) from +5V supply. How should I do
> that so that transients at +5V due to digital IC's are not coupled to +5V
> Analog ?.
>
> 2. Secondly, I require the impedance of power tracks not more than 0.1 Ohms
> at frequencies upto 50MHz. What should be the optimum dimensions of these
> tracks (+5V and its ground) ?.
>
> Also I 'ld appreciate if someone can guide me to an Application/Design note
> describing power/ground layout on a double-layer PCB for a multiple-supply
> instrument.
>
> I' ld be thankful to your response,
> Regards,
> Adeel Malik,
> Senior Design Engineer,
> Communications Enabling Technologies,
> 5-A Constitution Avenue,
> Islamabad, Pakistan.
> Tel: 92-51-2826160
> Fax: 92-51-2827469
>
--
National Semiconductor Corporation
2900 Semiconductor Drive, M/S 19-100
Santa Clara, California 95051
http://www.national.com/, NYSE: NSM
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