[SI-LIST] Re: Open Termination
- From: Sitar Moniker <si_monkey2@xxxxxxxxx>
- To: Prabhat.Agarwal@xxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Thu, 16 Sep 2004 11:37:42 -0700 (PDT)
Thank you, I liked your approach. I am tring to understand your explanation for
part 2) but have a question on part 1). A fF level cap gives a lot of
impedance. If freq is GHz order, impedance due to cap alone (1/fC) will be Mohm
order. I wonder isn't there an inductance of pH or even nH order lurking around
to pull down the resulting impedance (sqrt(L/C)) far from the infinite
neighborhood.
Prabhat.Agarwal@xxxxxxxxxxxx wrote:Dear Sitar,
1) The infinite impedance can be easily produced by just connecting a
small capactive load (in order of femto farad) at the termination point.
Today most of the VLSI circuits are MOS based, and their gate terminal
is driven by these transmission lines(PCB traces), which is an
unterminated case. These terminals offers very small capacitances to the
lines.
2)The intuitive understanding for voltage getting doubled on an
unterminated loss less line can be easily explained by considering
simple LC model.
As we all know that a loss less Transmission line is modelled as
distributed L & C.=20
Just consider one such LC segment, say first L and then C in series(
capacitor to ground), Output is taken across capacitor.
Analysis goes like this,
Supposing there is no energy stored initially, and you have connected a
voltage source 'V' at the inductor terminal. Inductor sees a positive
voltage across its terminals and current starts rising and in the
process charging the capacitor. At every instant the voltage across
inductor is decreasing, and di/dt is positive( but decreasing
continuously ) and current value keep increasing unless the capacitor
charges to voltage 'V'. At this instant the current through inductor
reaches it's peak amplitude(positive). Inductor by its inherent nature
tries to maintain that current in the same direction, but in doing so
charges the capacitor further. The inductor sees a negative voltage now
and current starts decreasing. The capacitor is kept charging above 'V'.
Imagine the current waveform vs time, when the current reaches its peak
value, the area under this curve is the total charge that got dumped on
to the capacitor producing a voltage 'V' across capacitor. Similarly
when this current starts decreasing from this point to zero, agin the
same amount of charge is dumped, thus producing a voltage 'V' above 'V'
which '2V'.
Thus you can further extend this analysis for distributed LC network.
This will also help you understand the reason for propagation delay of
the line, which is nothing but time required to charge these
capacitances.
Best wishes and regards
Prabhat Agarwal
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Sitar Moniker
Sent: Wednesday, September 15, 2004 3:18 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Open Termination
In SI and HSDD books, they assume that open termination offers infinite
impedance. My understanding is open end line is exposed to air which has
about 377 ohms.=20
=20
1) How do you get infinite impedance for unterminated line?=20
=20
2) Is there any intuitive way to show that voltage at the open end
doubles- other than using math: ref. coeft. =3D +1?
=20
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