[SI-LIST] Re: IBIS model for CML differential buffers

Fabrizio and Mohammad,

CML buffers up to 3.125 Gbps can and have been modeled in IBIS 
effectively.  At DesignCon 2002, Chris Brewster of SiQual presented a 
paper on buffer correlation between Hspice and Cadence SpecctraQuest. 
 There were no issues with driver output model correlation.  All 
correlation issues were concerned with lossy trace model discrepancies 
between SpecctraQuest and Hspice.  I believe that these Cadence issues 
have now been resolved.  As differential buffers become faster, it is 
actually easier to model them in IBIS, since these drivers have to be 
operating mostly in the linear region in order to operate at these 
extreme speeds and edge rates.  IBIS models are always best and most 
faithful when extracted from linear drivers.  Also, since the buffers 
are operating differentially, the influence of SSO is minimized. 
 Current starvation effects and pre-driver modulation effects are 
greatly reduced over their single-ended counterparts.  Any issues in 
simulation at these speeds is usually due to improper modeling of 
packages, vias, connectors, return-paths, and losses in the system.  

(As a side note, my research, simulations and measurements indicate that 
via-coupling in the driver BGA breakout region and in the region of the 
first connector insertion tend to have the most detremental effect on 
these high-speed signals.  These effects are often not modeled at all, 
or are modeled inappropriately or incorrectly by Signal Integrity 
simulators and extractors and/or engineers performing simualtion and 
modeling of differential systems.)

Having said this, it is not "fun" to extract these IBIS models and it 
can be quite time consuming to do so.  A more sane approach that I often 
use is to create a synthetic behavorial driver in hspice using voltage 
sources (or current sources), input waveshaping filters, a VCVS for 
output swing adjustment and a resistor to approximate the output 
impedance of the device, and then perform an optimization of the circuit 
to reproduce the original spice output waveform of the driver.  This 
usually takes less time than performing a differential IBIS model 
extraction and is incredibly fast in simulation.

In either case, preemphasis is not easily modeled.  It is possible to 
use multistage driver models in IBIS to perform pre-emphasis 
 simulation.  This works quite well, since pre-emphasis is generally an 
increase in the output signal swing on the leading edge of a bit pattern 
and can be approximated nicely by a timed multistage pulse.  

Several companies have the ability to model these differential devices: 
 SiSoft, SiQual, Mentor and Teraspeed.  We can actually extract the 
models from measurment, and have done so in the past for some 10 Gbps 
devices.  In some cases, the silicon vendor prefers IBIS measurement 
based models to Hspice models, because of the increased accuracy of the 
measurements.  We have modeled devices with risetimes in the 30 to 50 ps 
range.

best regards,

Scott

-- 
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com





Fabrizio Zanella wrote:

>Mohammad, I don't believe modeling CML differential buffers in the IBIS
>format can be done yet.  The speeds are extremely fast, 2.5 to 3.125Gbs,
>with sub-100ps risetimes, so the accuracy of transistor models is
>required. Also just about all CML I/O have various levels of transmitter
>pre-emphasis and/or receiver equalization, which is not handled by the
>IBIS spec today.
>My suggestion is to use spice models.
>Regards,
>
>Fabrizio Zanella
>Signal Integrity Engineer
>Broadbus Technologies
>fabrizioz@xxxxxxxxxxxx
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Mohammad Ali
>Sent: Wednesday, November 06, 2002 7:22 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] IBIS model for CML differential buffers
>
>
>Dear SI members,
>
>Can anybody point me to some resource links (any article, paper or
>presentations) where I can find some helpful information on how to
>accurately generate IBIS models (pullup, pulldown, PC, GC etc.) for
>CML (current mode logic) differential buffers? So far I have 
>succefully created models for TTL, CMOS and LVDS buffers operating 
>upto 622 Mb/s range. IBIS official websites and some EDA vendors
>websites and discussion pages have some model development topics, 
>but none of them about CML technology. 
>
>Hazem Hegazy from Mentor Graphics and Arpad Muranyi from Intel 
>delivered excellent articles and presentations on LVDS modeling. I
>am looking for something like those but on CML technologies.
>
>Any helpful hints or links would be highly appreciated. Thanks.
>
>-Mohammad Ali
>
>  
>


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