[SI-LIST] Re: IBIS model for CML differential buffers

I agree with all of the preceding discussion.  Additionally BIRD 73.4 =
was incorporated into IBIS 4.0.  This provides the functionality for =
modeling pre-emphasis or fallback models.

=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
Lawrence C. Barnes
Principal Signal Integrity Engineer
QLogic Corporation
2660 Laguna Hills Drive
Aliso Viejo, CA  92656
larry.barnes@xxxxxxxxxx


-----Original Message-----
From: Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
Sent: Wednesday, November 06, 2002 12:25 PM
To: fabrizioz@xxxxxxxxxxxx
Cc: mohammad.ali@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: IBIS model for CML differential buffers



Fabrizio and Mohammad,

CML buffers up to 3.125 Gbps can and have been modeled in IBIS=20
effectively.  At DesignCon 2002, Chris Brewster of SiQual presented a=20
paper on buffer correlation between Hspice and Cadence SpecctraQuest.=20
 There were no issues with driver output model correlation.  All=20
correlation issues were concerned with lossy trace model discrepancies=20
between SpecctraQuest and Hspice.  I believe that these Cadence issues=20
have now been resolved.  As differential buffers become faster, it is=20
actually easier to model them in IBIS, since these drivers have to be=20
operating mostly in the linear region in order to operate at these=20
extreme speeds and edge rates.  IBIS models are always best and most=20
faithful when extracted from linear drivers.  Also, since the buffers=20
are operating differentially, the influence of SSO is minimized.=20
 Current starvation effects and pre-driver modulation effects are=20
greatly reduced over their single-ended counterparts.  Any issues in=20
simulation at these speeds is usually due to improper modeling of=20
packages, vias, connectors, return-paths, and losses in the system. =20

(As a side note, my research, simulations and measurements indicate that =

via-coupling in the driver BGA breakout region and in the region of the=20
first connector insertion tend to have the most detremental effect on=20
these high-speed signals.  These effects are often not modeled at all,=20
or are modeled inappropriately or incorrectly by Signal Integrity=20
simulators and extractors and/or engineers performing simualtion and=20
modeling of differential systems.)

Having said this, it is not "fun" to extract these IBIS models and it=20
can be quite time consuming to do so.  A more sane approach that I often =

use is to create a synthetic behavorial driver in hspice using voltage=20
sources (or current sources), input waveshaping filters, a VCVS for=20
output swing adjustment and a resistor to approximate the output=20
impedance of the device, and then perform an optimization of the circuit =

to reproduce the original spice output waveform of the driver.  This=20
usually takes less time than performing a differential IBIS model=20
extraction and is incredibly fast in simulation.

In either case, preemphasis is not easily modeled.  It is possible to=20
use multistage driver models in IBIS to perform pre-emphasis=20
 simulation.  This works quite well, since pre-emphasis is generally an=20
increase in the output signal swing on the leading edge of a bit pattern =

and can be approximated nicely by a timed multistage pulse. =20

Several companies have the ability to model these differential devices:=20
 SiSoft, SiQual, Mentor and Teraspeed.  We can actually extract the=20
models from measurment, and have done so in the past for some 10 Gbps=20
devices.  In some cases, the silicon vendor prefers IBIS measurement=20
based models to Hspice models, because of the increased accuracy of the=20
measurements.  We have modeled devices with risetimes in the 30 to 50 ps =

range.

best regards,

Scott

--=20
Scott McMorrow
Teraspeed Consulting Group LLC
2926 SE Yamhill St.
Portland, OR 97214
(503) 239-5536
http://www.teraspeed.com





Fabrizio Zanella wrote:

>Mohammad, I don't believe modeling CML differential buffers in the IBIS
>format can be done yet.  The speeds are extremely fast, 2.5 to =
3.125Gbs,
>with sub-100ps risetimes, so the accuracy of transistor models is
>required. Also just about all CML I/O have various levels of =
transmitter
>pre-emphasis and/or receiver equalization, which is not handled by the
>IBIS spec today.
>My suggestion is to use spice models.
>Regards,
>
>Fabrizio Zanella
>Signal Integrity Engineer
>Broadbus Technologies
>fabrizioz@xxxxxxxxxxxx
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx =
[mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Mohammad Ali
>Sent: Wednesday, November 06, 2002 7:22 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] IBIS model for CML differential buffers
>
>
>Dear SI members,
>
>Can anybody point me to some resource links (any article, paper or
>presentations) where I can find some helpful information on how to
>accurately generate IBIS models (pullup, pulldown, PC, GC etc.) for
>CML (current mode logic) differential buffers? So far I have=20
>succefully created models for TTL, CMOS and LVDS buffers operating=20
>upto 622 Mb/s range. IBIS official websites and some EDA vendors
>websites and discussion pages have some model development topics,=20
>but none of them about CML technology.=20
>
>Hazem Hegazy from Mentor Graphics and Arpad Muranyi from Intel=20
>delivered excellent articles and presentations on LVDS modeling. I
>am looking for something like those but on CML technologies.
>
>Any helpful hints or links would be highly appreciated. Thanks.
>
>-Mohammad Ali
>
> =20
>


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