Posts for si-list, 11-2002

Browse: Last Month: 10-2002 Main Archive Page Next Month: 12-2002

» [SI-LIST] Re: Via/Contact Resisance? -
» [SI-LIST] Re: Power supply noise -
» [SI-LIST] Power supply noise -
» [SI-LIST] Via/Contact Resisance? -
» [SI-LIST] Re: How to select the pullup/pulldwon resistor -
» [SI-LIST] Re: How to select the pullup/pulldwon resistor -
» [SI-LIST] Re: How to select the pullup/pulldwon resistor -
» [SI-LIST] Star-Hspice working directory -
» [SI-LIST] Re: Seeking sources for hard-2-find tech books -
» [SI-LIST] How to select the pullup/pulldwon resistor -
» [SI-LIST] compact-PCI clock generation -
» [SI-LIST] dear sir,=20 -
» [SI-LIST] Fwd: RE: harmonics -
» [SI-LIST] Re: Please suggest a way to monitor high speed busses -
» [SI-LIST] Yet another HSPICE error message -
» [SI-LIST] Re: Please suggest a way to monitor high speed busses -
» [SI-LIST] Re: transformer -
» [SI-LIST] Please suggest a way to monitor high speed busses -
» [SI-LIST] Re: Seeking sources for hard-2-find tech books -
» [SI-LIST] Re: mailed you an e-card -- Si-List. WARNING about Virus in previous message with this subject. -
» [SI-LIST] Re: Error in HSPICE -
» [SI-LIST] Re: transformer -
» [SI-LIST] Re: transformer -
» [SI-LIST] Re: Error in HSPICE -
» [SI-LIST] Re: compact PCI clock frequency -
» [SI-LIST] compact PCI clock frequency -
» [SI-LIST] Re: Error in HSPICE -
» [SI-LIST] Re: Error in HSPICE -
» [SI-LIST] problem -
» [SI-LIST] transformer -
» [SI-LIST] harmonics -
» [SI-LIST] AW: How to make SPICE model of bead -
» [SI-LIST] Error in HSPICE -
» [SI-LIST] Re: Multiple Job Opportunities -
» [SI-LIST] position available -
» [SI-LIST] Re: Seeking sources for hard-2-find tech books -
» [SI-LIST] Re: Seeking sources for hard-2-find tech books -
» [SI-LIST] FW: Seeking sources for hard-2-find tech books use www.addall.com -
» [SI-LIST] Re: Seeking sources for hard-2-find tech books -
» [SI-LIST] Re: Seeking sources for hard-2-find tech books -
» [SI-LIST] Seeking sources for hard-2-find tech books -
» [SI-LIST] MICROVIA CAPACITANCE -
» [SI-LIST] SORRRY, VIRUS. -
» [SI-LIST] mailed you an e-card -- Si-List. -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Creating Pseudo Random Bit Sequence (PRBS) stimuli for Hspice -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Creating Pseudo Random Bit Sequence (PRBS) stimuli for Hspice -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Creaging Pseudo Random Bit Sequence (PRBS) stimuli for Hspice -
» [SI-LIST] All you want for Xmas is to sim at Dell, Dude.... -
» [SI-LIST] Re: Theoretical Battery Life -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Cascading differential 2-Port Networks -
» [SI-LIST] Re: Cascading differential 2-Port Networks -
» [SI-LIST] Re: Creaging Pseudo Random Bit Sequence (PRBS) stimuli for Hspice -
» [SI-LIST] HSTL technology -
» [SI-LIST] Re: Cascading differential 2-Port Networks -
» [SI-LIST] FW: Impedance / stackup calculations and ApsimRLGC -
» [SI-LIST] Re: Creating Pseudo Random Bit Sequence (PRBS) stimulifor Hspic -
» [SI-LIST] Re: Creating Pseudo Random Bit Sequence (PRBS) stimuli for Hspic -
» [SI-LIST] Re: more on PWL statement generation for PRBS simul atio n in spice -
» [SI-LIST] AW: Re: more on PWL statement generation for PRBS simulatio n in spice -
» [SI-LIST] Re: more on PWL statement generation for PRBS simulation in spice -
» [SI-LIST] Home-brewed Power-Over-Ethernet? OT? -
» [SI-LIST] Cascading differential 2-Port Networks -
» [SI-LIST] [IBIS-Users] IBIS Questions -
» [SI-LIST] PCB layout: How to choose allowable crosstalk? -
» [SI-LIST] for design and high speed engg -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] more on PWL statement generation for PRBS simulation in spice -
» [SI-LIST] Re: Creaging Pseudo Random Bit Sequence (PRBS) stimuli for Hspice -
» [SI-LIST] Creaging Pseudo Random Bit Sequence (PRBS) stimuli for Hspice -
» [SI-LIST] Re: Home-brewed Power-Over-Ethernet? OT? -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: PCI-spec question -
» [SI-LIST] Home-brewed Power-Over-Ethernet? OT? -
» [SI-LIST] Re: PCI-spec question -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] PCI-X in Specctraquest -
» [SI-LIST] Re: Theoretical Battery Life -
» [SI-LIST] Theoretical Battery Life -
» [SI-LIST] Re: question about using headers in power distribution ? -
» [SI-LIST] Re: question about using headers in power distribution ? -
» [SI-LIST] Re: Diode in test load -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: A question about ansoft -
» [SI-LIST] Re: Diode in test load -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Diode in test load -
» [SI-LIST] question about using headers in power distribution ? -
» [SI-LIST] A question about ansoft -
» [SI-LIST] QQuestion: Radiation, in inquiry time of Terminator value ? -
» [SI-LIST] COnsecutive 0's or 1's in 4b5b encoded data -
» [SI-LIST] Signal Integrity Classes: December -
» [SI-LIST] Re: Advise on PCB dessign software -
» [SI-LIST] Sorry incorrect forum.... -
» [SI-LIST] Layout to allegro -
» [SI-LIST] Advise on PCB dessign software -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] SABER parts to PSpice parts -
» [SI-LIST] Re: Allegro Question -
» [SI-LIST] RMCEMC November Meeting Reminder & Restaurant update -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Allegro Question -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: Softwares & IBIS questions... -
» [SI-LIST] pc2700 simulation models -
» [SI-LIST] T1/E1 Tutorial published ! -
» [SI-LIST] T1/E1 Tutorial published ! -
» [SI-LIST] running rlgc file - conclusion...and special thanks to you matt -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Pictures of TC77b meeting in Arizona -
» [SI-LIST] Re: differential signaling terminator. -
» [SI-LIST] IBIS Model and how to model PCB Trace & minimize cross talk -
» [SI-LIST] differential signaling terminator. -
» [SI-LIST] bring files from Pspice 8 to Pspice 9.1 -
» [SI-LIST] Bus length -
» [SI-LIST] Re: ECL or LVDS? -
» [SI-LIST] Re: GMII over Board-to-Board Connector -
» [SI-LIST] Re: GMII over Board-to-Board Connector -
» [SI-LIST] GMII over Board-to-Board Connector -
» [SI-LIST] ECL or LVDS? -
» [SI-LIST] Re: signal source distribution and jitter question -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: signal source distribution and jitter question -
» [SI-LIST] Re: Surface mount SMB -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] Re: signal source distribution and jitter question -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] Re: Effect of Stub-Length on Max. Length Calculation -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] QQuestion: DC Ohm's law , rot E is zero ? at wire surface -
» [SI-LIST] Effect of Stub-Length on Max. Length Calculation -
» [SI-LIST] Re: flight time = propagation delay? -
» [SI-LIST] flight time = propagation delay? -
» [SI-LIST] Re: A question about XTK -
» [SI-LIST] Re: Surface mount SMB -
» [SI-LIST] A question about XTK -
» [SI-LIST] Re: Sample Projects or Designs for Mentor Graphics ICX Tool -
» [SI-LIST] Re: Surface mount SMB -
» [SI-LIST] How to make SPICE model of bead -
» [SI-LIST] Re: Surface mount SMB -
» [SI-LIST] signal source distribution and jitter question -
» [SI-LIST] Sample Projects or Designs for Mentor Graphics ICX Tool -
» [SI-LIST] Re: Surface mount SMB -
» [SI-LIST] Dynamic Clamp -
» [SI-LIST] PCI I/O design -
» [SI-LIST] Surface mount SMB -
» [SI-LIST] ASIC core level and package level SI issues. -
» [SI-LIST] Re: Surface mount vs. through hole at 1.5 to 3 Gbps -
» [SI-LIST] Re: Flight Time -
» [SI-LIST] Re: Flight Time -
» [SI-LIST] Re: Flight Time -
» [SI-LIST] Re: Flight Time -
» [SI-LIST] Re: Flight Time -
» [SI-LIST] Re: Flight Time -
» [SI-LIST] Flight Time -
» [SI-LIST] Re: The stimulus rise/fall time in hspice -
» [SI-LIST] Re: Traces under converters - bad mojo or myth? -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] EDN Access 09.01.95 Don't let rules of thumb set decoupling-capacitor values -
» [SI-LIST] Re: The stimulus rise/fall time in hspice -
» [SI-LIST] Re: The stimulus rise/fall time in hspice -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Close field measurement method -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Books for Mixed-Mode S matrix -
» [SI-LIST] Re: running rlgc file -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] running rlgc file -
» [SI-LIST] Re: Effect of contact resistance on high frequency signals -
» [SI-LIST] The stimulus rise/fall time in hspice -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Surface mount vs. through hole at 1.5 to 3 Gbps -
» [SI-LIST] Surface mount vs. through hole at 1.5 to 3 Gbps -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Meeting Notice, tonight, Santa Clara Valley EMC Chapter -
» [SI-LIST] Re: Books for Mixed-Mode S matrix -
» [SI-LIST] Effect of contact resistance on high frequency signals -
» [SI-LIST] Re: Registered DDR 266/333 model? -
» [SI-LIST] Re: Books for Mixed-Mode S matrix -
» [SI-LIST] Re: Books for Mixed-Mode S matrix -
» [SI-LIST] Books for Mixed-Mode S matrix -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Registered DDR 266/333 model? -
» [SI-LIST] Re: Decoupling of Oscillator -
» [SI-LIST] Re: Decaps. in a BGA package..?? -
» [SI-LIST] octal Gigabit Ethernet PHY -
» [SI-LIST] Re: Registered DDR 266/333 model? -
» [SI-LIST] Decoupling of Oscillator -
» [SI-LIST] Re: Registered DDR 266/333 model? -
» [SI-LIST] Re: Power/Ground Net modeling in TPA ... -
» [SI-LIST] Signal Interface within CML and LVDS? -
» [SI-LIST] Registered DDR 266/333 model? -
» [SI-LIST] Re: IBIS model for CML differential buffers -
» [SI-LIST] Clock net correlation_current mode current steeling -
» [SI-LIST] Power/Ground Net modeling in TPA ... -
» [SI-LIST] Re: signal to noise ratio of a connector -
» [SI-LIST] Re: IBIS Model monotonocity and ICX and ibischk -
» [SI-LIST] Re: signal to noise ratio of a connector -
» [SI-LIST] Re: IBIS Model monotonicity and ICX and ibischk -
» [SI-LIST] Re: IBIS Model monotonocity and ICX and ibischk -
» [SI-LIST] Re: IBIS Model monotonocity and ICX and ibischk -
» [SI-LIST] Re: signal to noise ratio of a connector -
» [SI-LIST] Re: IBIS Model monotonocity and ICX and ibischk -
» [SI-LIST] IBIS Model monotonocity and ICX and ibischk -
» [SI-LIST] Softwares & IBIS questions... -
» [SI-LIST] signal to noise ratio of a connector -
» [SI-LIST] Re: IBIS model for CML differential buffers -
» [SI-LIST] About Software and IBIS question -
» [SI-LIST] Re: floating metals -
» [SI-LIST] floating metals -
» [SI-LIST] Re: Recruiter Postings -
» [SI-LIST] Re: PCI : 5V clock to non-5V tolerant clock input -
» [SI-LIST] Recruiter Postings -
» [SI-LIST] Signal Integrity Position in our team -
» [SI-LIST] Re: Equalization of transmission lines? -
» [SI-LIST] Re: Decaps. in a BGA package..?? -
» [SI-LIST] Re: Decaps. in a BGA package..?? -
» [SI-LIST] Decaps. in a BGA package..?? -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] si Engineer -
» [SI-LIST] FW: Off Topic Question -
» [SI-LIST] Re: PCI : 5V clock to non-5V tolerant clock input -
» [SI-LIST] Re: which one is better -
» [SI-LIST] Re: Basic IBIS I/V curve question -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] PCI : 5V clock to non-5V tolerant clock input -
» [SI-LIST] Re: Equalization of transmission lines? -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] Re: Off Topic Question -
» [SI-LIST] Off Topic Question -
» [SI-LIST] Re: Equalization of transmission lines? -
» [SI-LIST] Re: Equalization of transmission lines? -
» [SI-LIST] Re: Equalization of transmission lines? -
» [SI-LIST] Equalization of transmission lines? -
» [SI-LIST] Re: Basic IBIS I/V curve question -
» [SI-LIST] Re: Voltage Drop -
» [SI-LIST] Voltage Drop -
» [SI-LIST] Re: Basic IBIS I/V curve question -
» [SI-LIST] Re: Basic IBIS I/V curve question -
» [SI-LIST] Re: Basic IBIS I/V curve question -
» [SI-LIST] Re: Basic IBIS I/V curve question -
» [SI-LIST] Basic IBIS I/V curve question -
» [SI-LIST] Re: HSPICE & Common Model Interface -
» [SI-LIST] Hysteresis in LVDS receiver. -
» [SI-LIST] Re: HSPICE & Common Model Interface -
» [SI-LIST] Re: Off topic - IC package marking -
» [SI-LIST] Off topic - IC package marking -
» [SI-LIST] Re: HSPICE & Common Model Interface -
» [SI-LIST] Re: IBIS model for CML differential buffers -
» [SI-LIST] Re: IBIS model for CML differential buffers -
» [SI-LIST] Re: IBIS model for CML differential buffers -
» [SI-LIST] Re: Smartspice vs Hspice? -
» [SI-LIST] Hspice problems with [Driver_Schedule] IBIS buffers -
» [SI-LIST] Re: About IBIS error from IBIS check -
» [SI-LIST] IBIS model for CML differential buffers -
» [SI-LIST] backplane docs link -
» [SI-LIST] Re: about ABT tech and a basic question -
» [SI-LIST] Re: MEASUREMENT OF POWER-DISTRIBUTION NETWORKS AND ITS ELEMENTS -
» [SI-LIST] About IBIS error from IBIS check -
» [SI-LIST] Smartspice vs Hspice? -
» [SI-LIST] Re: EMI/EMC software -
» [SI-LIST] Re: Capacitance Formula -
» [SI-LIST] Re: Capacitance Formula -
» [SI-LIST] John Cooley article in EE Times -
» [SI-LIST] Re: Capacitance Formula -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: DC resistance calculation of returen path_equivalent width? -
» [SI-LIST] Re: DC resistance calculation of returen path_equivalent width? -
» [SI-LIST] MEASUREMENT OF POWER-DISTRIBUTION NETWORKS AND ITS ELEMENTS -
» [SI-LIST] SI Contractor Position Opening -
» [SI-LIST] about ABT tech and a basic question -
» [SI-LIST] Re: spatial resolution and effective rise time of VNA with TDR time-domain option -
» [SI-LIST] Re: Via-In-Pad or Via-Next-To-Pad - which is best? -
» [SI-LIST] Re: Capacitance Formula -
» [SI-LIST] Re: Capacitance Formula -
» [SI-LIST] Re: Capacitance Formula -
» [SI-LIST] Re: Via-In-Pad or Via-Next-To-Pad - which is best? -
» [SI-LIST] Re: AC Analysis in Hspice -
» [SI-LIST] Re: AC Analysis in Hspice -
» [SI-LIST] Re: What it takes to be a Signal Integrity Expert -
» [SI-LIST] Via-In-Pad or Via-Next-To-Pad - which is best? -
» [SI-LIST] DC resistance calculation of returen path_equivalent width? -
» [SI-LIST] Audio Amplifier -
» [SI-LIST] doing measurements in Hspice -
» [SI-LIST] Re: What it takes to be a Signal Integrity Expert -
» [SI-LIST] Re: AC Analysis in Hspice -
» [SI-LIST] Measuring volgage across seams -
» [SI-LIST] Presentation available for download & November Meeting - Take2 -
» [SI-LIST] Presentation available for download & November Meeting -
» [SI-LIST] FYI: Article on Spintronics--Microelectronic devices that function by using spin of the electron -
» [SI-LIST] Re: What it takes to be a Signal Integrity Expert -
» [SI-LIST] What it takes to be a Signal Integrity Expert -
» [SI-LIST] Re: AC Analysis in Hspice -
» [SI-LIST] AC Analysis in Hspice -
» [SI-LIST] Physical layer design/test position -
» [SI-LIST] Re: Why we need to use "Series resistor" at Transmi tter? -
» [SI-LIST] Re: FET Probe -
» [SI-LIST] Re: FET Probe -