[SI-LIST] How good is enough(Power Integrity)
- From: zhangkun 29902 <zhang_kun@xxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Fri, 23 Apr 2004 14:00:17 +0800
Dear All
How good is enough in power integrity analysis at PCB level?
In my experience, for some kind of general chip such as SDRAM, even there is no
decoupling caps for SDRAM, they will work well. However, for some chips, the
power ground noise is very critical.
In signal integrity, there are plenty of model to simulate. In power integrity,
how to do?
Any advice will be prefered.
Best Regards
Zhangkun
2004.4.23
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