[SI-LIST] Re: HSPICE and Via Modeling
- From: Ravinder.Ajmani@xxxxxxxxxxxxxx
- To: si-list@xxxxxxxxxxxxx
- Date: Mon, 18 Jul 2005 14:09:25 -0700
Even if the edge rate is 50 ps, signal degradation due to via will only be
critical for GHz range signals, and should not matter for the 5 MHz
signal. So I think Chris Cheng is correct to suggest using first order
approximation.
Regards, Ravinder
Server PCB Development
Hitachi Global Storage Technologies
Email: Ravinder.Ajmani@xxxxxxxxxxxxxx
"Mirmak, Michael" <michael.mirmak@xxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
07/18/2005 01:50 PM
Please respond to
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[SI-LIST] Re: HSPICE and Via Modeling
And if the 5 MHz signal has a 50 ps edge rate...?
I realize this is an extreme example. However, increasingly we are
seeing allegedly "slow" interfaces with low using buffers of extremely
high edge rate. Without knowing the edge rate here, I'm not sure we can
categorically recommend a lumped capacitance model as appropriate.
- Michael Mirmak
Intel Corp.
Chair, EIA IBIS Open Forum
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Chris Cheng
Sent: Monday, July 18, 2005 1:41 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE and Via Modeling
I highly doubt you need HFSS for a 5MHz design.
Get you blind via dimensions and use a first order approximation of a =
=3D
coxial cylinder for the capacitance and you should be GTG.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Leonard Dieguez
Sent: Monday, July 18, 2005 1:27 PM
To: david.lieby@xxxxxxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: HSPICE and Via Modeling
David,
I have never been very good at coming up with closed form equations for
problems like that. I would create a 3D EM model in HFSS. This would
model the stackup, board materials and via placement including the
ground vias in the area or the return vias. Run the simulation over a
representative band of frequencies and generate S-parameters. You can
then import the S-parameters into Hspice or other time domain
simulators with the other circuits and run your simulations. Before
doing that I would optimize the via diameter, anti pad clearance,
annular ring diameter, distance from ground / return via and trace
thickness over anti-pad for the desired impedance matching. The
optimization can be done in HFSS. By looking at the return loss and
insertion loss over the frequency band will give you an idea how the via
will behave. In general vias have a tendency to have a excess
capacitance when compared to the trace connecting to it.
Leonard Dieguez
Xilinx System IO Specialist
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of dav0
Sent: Monday, July 18, 2005 11:28 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] HSPICE and Via Modeling
I have an engineer who wants a detailed model of a via.
Mostly he is looking for capacitance. The part of the system he is
working on runs at less than 5 MHz. The via is blind, with the closed
end of the via ending fairly close to a ground plane.
__ __ Top Pad
________ ][ _____ Reference layer
][
---------][----- routing layer 1
---------][----- routing layer 2
________ ][ _____ Reference layer
][
---------][----- routing layer 3
---------][----- routing layer 4
________ ][ _____ Reference layer
][
---------][----- routing layer 5
---------][----- routing layer 6
__][__ Bottom pad, end of via
_________________ Reference layer, at center of stackup
the same stackup reversed.
My questions:
1. Can one analyze this in HSPICE?
2. Does anyone have a spice deck with anywhere near
a starting point, that they can share.
The vendor support engineer could not come up with anything helpful.
Thanks,
dav0
David Lieby
Siemens Medical, USD, MVIS-S
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- References:
- [SI-LIST] Re: HSPICE and Via Modeling
- From: Mirmak, Michael
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- » [SI-LIST] Re: HSPICE and Via Modeling
- [SI-LIST] Re: HSPICE and Via Modeling
- From: Mirmak, Michael