[SI-LIST] Re: GND Separation for Analog & Digital circuits
- From: "Ken Cantrell" <Ken.Cantrell@xxxxxxxxxxxxxxxx>
- To: <Chris.Cheng@xxxxxxxxxxxx>, <jrbarnes@xxxxxxxxx>,<si-list@xxxxxxxxxxxxx>
- Date: Fri, 27 Feb 2004 08:43:54 -0700
John,
I think we are all interested in what you have to say, but I concur with
Chris:
"ps If you want to respond to this discussion, please don't add
any more non-relevant biography about yourself or your book. Let's
focus on the technical discussion."
Ken
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Chris Cheng
Sent: Thursday, February 26, 2004 9:31 PM
To: 'jrbarnes@xxxxxxxxx'; Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: GND Separation for Analog & Digital circuits
I have cut a lot of your advertisements from the thread to continue
this discussion. Let's focus on the technical side rather than
what kind of service you provide and book you want to sell.
It is one thing to do mesh planes in the 80's where bus speed is
from a few to ten's of MHz if you are high tech. It is another
thing to design a 2GHz speed system with it. I am shock you can
even equate the two.
Scott has made a good summary that I happen to agree on what is the
problems with mesh plane routing strategy, I suggest you go back
and read it and learn something about these problems in true high
speed design.
Like you said, IBM has been doing it in the 70's and 80's.
They are well aware of the trade-offs in the design. I have
personally talked to Evan Davidson who is Mr. TCM in IBM. The
first thing he will tell you is this is a process trade-off
rather than performance enhancement. It makes highspeed interconnect
almost impossible to predict without a custom CAD design structure
that can handle the complex problem associated with the signal
path and return current along the propagation path. When you have
a meshed reference structure, the normal ideal transmission line
model you use is out the door. You now have to analyze the return
path also as a 3-d structure together with the vias that is needed
to propagate the signal and its reference (as a trace). When all is
said and done, you will end up needing three times the via as
regular plane since every time your signal switch, you reference
traces need to do so. Worst, they have to be close to each other
otherwise and you need to have the same reference trace on the
orthogonal layer to take up the current. Things get even worst
when multiple signals comes in an out of the layer and needing
vias on the same poor reference trace which will be drill to nothing.
Not to mention the image current is forced to overlap each other
on the reference trace and therefore increase your crosstalk.
IBM was so concern about it they have to develop PECC to handle
all these 3D interconnect and they swear by me that they simulate
every single one of their nets in 3D multiple coupled line form
to confirm their propagation. They also need custom CAD tools to
add the return vias every time signal get switched. Are you or
whoever propose this is ready to do this service to your
customers ? Do you even know how to do it ? Whatever paper
that reference to these mesh architecture for PCB says
nothing about these return current management. He is
either unaware of it or choose to ignore it to
minimum the 3x micro via requirement.
Like I said before, I have done ~GHz MCM buses with mesh planes.
I am well aware of these trade offs. The devil is in the details.
There is no way you can justify the trade-off in either cost (because
of the excess micro-vias required) and the performance (what
performance ? 10MHz or 50MHz ?).
ps If you want to respond to this discussion, please don't add
any more non-relevant biography about yourself or your book. Let's
focus on the technical discussion.
>To me, the major justification for meshing power and ground is cost.
>For commercial products like the ones that I have developed and helped
>develop for the last 31 years, saving a few dollars on the raw board
>cost may make the difference between putting a profitable product on the
>market, or trash-canning the whole project. For some of the products
>that I worked on, coming up with a $0.05 cost savings would force an
>mandatory engineering change. Adding 40% to the raw-board cost by using
>a 4-layer board instead of a double-sided board, or a 6-layer board
>instead of a 4-layer board, was unacceptable unless there was no other
>way to complete the project on schedule.
>
>I myself have not used the Power Mesh Architecture or the Interconnected
>Mesh Power System (IMPS). But they both look like reasonable extensions
>of the power/ground-gridding scheme that we have used at IBM Lexington
>and Lexmark since the early 1980's on double-sided and multilayer boards
>for:
>
>Internal Network Adapters (INA's) that I designed and developed in the
>mid-1990's, that were nearly 50% shrinks from relatively-dense External
>Network Adapters (ENA's). I cut the board size from roughly 7" x 4"
>down to 4.06" x 3.74", eliminating one parallel port and changing to a
>higher-density parallel connector. Each of these designs took 2 spins
>to go into production. These are both 4-layer boards, laid out using
>what we referred to as a "submerged trace" scheme:
>* Top and bottom of the board had components with traces just long
> enough to via into the two inner layers--the only exceptions were
> traces < 0.5" long that directly wired the ASIC to the processor.
>* We encircled each IC with ground, except for the ASIC and processor
> where the pair were encircled with ground.
>* Otherwise, we encircled each component or clump of components with
> ground.
>* Wherever possible, we had ground pads under the IC's, tied to the
> ground encircling the part through each ground pin of the IC, and to
> the inner layers anywhere we could fit a via.
>* The two inside layers had heavy power and ground grids, with ground
> traces running around the perimeter of the board (ground ring).
>* All signal wiring, except for the ASIC-to-processor traces mentioned
> above, was run in the inner two layers. Clocks were run next to
> ground traces, many of which had to be added manually. Since
> plated-through holes, vias, and mounting/tooling holes were the only
> things blocking these layers, we achieved very-high wiring density
> even with 0.006" lines and spaces, and relatively-large vias (cheap,
> cheap, cheap).
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