[SI-LIST] FW: diff pair routing at 10gig

Moshe,
        The XFP connector datasheets indicate that bare metal would be
        touching the board. If you use an insulator, it could be routed
        on the outer layer, but would add extra manual labor to install.
        
        I did not have this option, and routed using two vias. I tried
        to minimize any via stubs by routing the signal through most of
        the via barrel (see the attached picture) and created special 
        via padstack that had circular route keepouts in place of any 
        internal unconnected via pads.

P.S.    Also double check your BGA's. One the manufacturer's preliminary

        datasheets showed the BGA pin pitch at 1.27 mm, in reality it
        was 1.0 mm.

Regards,
       Mike Finczak
       CopperCAD Design
       www.CopperCAD.com
       905-488-8958


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Moshe Frid
Sent: Wednesday, May 30, 2007 4:19 AM
To: si-list
Subject: [SI-LIST] diff pair routing at 10gig


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Hello all

=20

Can someone help me with routing issue of diff pair at 10gig from serdes
chip to XFP connector=20

I have 2 options -=20

1. Rout in outer layer (cs) without vias with solder mask cover
reference plane in layer 2 (the traces will go under the xfp cage would
it be a problem)

2. Rout it in inner layer in strip line between to planes but with 2
vias per line=20

=20

What should work best for me

                    =20

thanks

________________________________

Moshe Frid=20
Senior PCB Designer=20

Adcom Computers and Communications Ltd.
17 Ha'Tidhar st., Ra'anana
Israel 43665
Tel: +(972)-9-7417411 ext. 108
Fax: +(972)-9-7417422
Mobile: +(972)-54-6573232
E-mail: moshef@xxxxxxxxxxx

  <http://www.adcom.co.il>=20

=20

=20




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