[SI-LIST] Re: FW: Embedded uStrip - double check me
- From: Paul Levin <levinpa@xxxxxxxxxxxxx>
- To: "'si-list@xxxxxxxxxxxxx'" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 06 Nov 2003 02:22:42 -0800
Dear All,
I just used LINPAR v2 on the problem. As mentioned, it allows one to use
a different value for K (and tan Delta) for each layer of dielectric, but
to have comparable results, I used 4.3 and 0.02 for both the dielectric
and the coating. Also, unless you are prepared to do a whole lot of hand
work, LINPAR assumes "level flooding" for each layer, i.e., the coating
looks like the first diagram below and not the second. It would also
require a whole lot of hand work in order to simulate a trapezoidal
cross section for the trace.
That said, this $399 tool predicts 50.60 ohms. Pretty nifty, huh?
Regards,
Paul
____________________
WALKER, Mark wrote:
> Bill, I've just done a couple of calculations using the polar Si6000b
> software (it seems to be the benchmark here in the UK) and I believe the
> problem may lie with the large trace thickness relative to the thin coating.
> A secondary effect is the trapezoidal shape of the trace cross-section;
> thinner at the top than the bottom, due to uneven etching. I believe it is
> usual to ignore this, but in your case the trace is relatively thick, so it
> is worth investigating. You can get an idea of the ratios of trace width at
> the trace's top & bottom using polar with a fixed impedance & clicking
> calculate for the top or bottom width. Your PCB vendor may also be able to
> offer wisdom on this.
>
> However, whilst we are on the subject of trace thickness / width, I wonder
> why you have such a skinny feature on a board's surface (ie. in such thick
> copper). I would expect your board fabricators to complain and point out
> that this will lead to low yield as these features are difficult to etch.
> Also, since they are on the pad layer, any scrap would be expensive as it
> has already had much of the processing done (ie. the board is nearly
> finished). It is safer to stick to just pads & fat meaty tracks on the
> surface. The only reasons I can think of are that you may desire minimum
> propagation delay, in which case you'd be better off without a coating, or
> you have very few layers. In any case it would be nice to know your
> reasoning for making life so difficult.
>
>
> Impedance calculations
> (dimensions in mills {called thou in the UK})
>
> Calcs were done with Polar Si6000B Quick Solver version 2.10 (dongle &
> license required). The applicable models are: coated microstrip, surface
> microstrip and embedded microstrip. The models seem to assume that the track
> is thin in comparison to the coating and have a uniform cross-section for
> the board, like this:
>
> --------------------------------------------
> coating
> ___________
> | track |
> --------------------------------------------
>
> dielectric
>
> --------------------------------------------
>
> plane
>
>
>
>
> what I think you have is a 'hump' on the surface, due to the trace's large
> thickness, like this
>
>
>
> _______________
> / ___________ \
> __________/ | track | \_______________
> coating | |
> --------------------------------------------
>
> dielectric
>
> --------------------------------------------
>
> plane
>
>
> Coated microstrip
> H 4
> H1 0.8
> W 5
> W1 5
> T 2.1
> Er 4.3
> Zo 50.09 (calculated)
>
> Surface microstrip
> H 4
> H1 N/A (no coating)
> W 5
> W1 5
> T 2.1
> Er 4.3
> Zo 56.49 (calculated)
>
> Embedded microstrip
> H 6.9 (4 + 2.1 + 0.8)
> H1 4
> W 5
> W1 5
> T 2.1
> Er 4.3
> Zo 50.09 (calculated)
>
>>From the similarity between the coated & embedded microstrip, it looks like
> the software is assuming the coating has the same Er as the dielectric,
> which I should think is wrong. The dielectric coating is obviously having an
> effect because the surface microstrip (which has no dielectric material
> above it) has a significantly different Zo. There are more advanced (and no
> doubt expensive) versions of the software available, which may allow a
> separate Er for the coating and a non-uniform cross-section. We also have
> LinPar here, but I have not used it much. I believe there are free field
> solvers about the web. A quick Google search should deliver, it just depends
> on your priorities & available time.
>
> If you can, just stick to pads & fat traces on the pad layer. If you must
> have real skinny traces on the pad layer and can't make the copper any
> thinner or dielectric any thicker, you are going against conventional wisdom
> and making life difficult so you will have to go the extra mile to ensure
> you get what you want.
>
> Also remember that PCB fabrication is not yet an exact science and most
> vendors will only guarantee impedance to an accuracy of +/- 10% anyway,
> although this is usually good enough, provided the nominal value is correct
> to start with.
>
> Regards,
> Mark.
>
> Astrium-Space,
> Stevenage,
> England.
>
> -----Original Message-----
> From: bdempsey85 [mailto:bdempsey85@xxxxxxxxxxx]
> Sent: 06 November 2003 12:40:AM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Embedded uStrip - double check me
>
>
> I would like a double check on my coated uStrip impedance calculations.
> I am getting feedback from my PCB fabricator that my numbers are >10%
> off.
>
> Here are the parameters:
> 5 mil wide trace, 0.5 foil with add'l 1oz plating (approx 2.1 mils
> thickness)
> 4 mil trace to plane, Er ~ 4.3
> LPI soldermask ~ 0.8 mils thick
>
> I compute 51 ohms...how about you?
>
> Thanks,
> Bill
>
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--
Paul Levin
Senior Principal Engineer
Xyratex Storage Systems
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