Suppose there is a differential pair highly coupled with 100 diff. impedance routed on a PCB. Suppose there is an obstacle in the way such that the pair must be split for time, thus incurring an impedance mismatch. Is there a general rule of thumb for acceptable impedance mismatch that correlates the propagation delay of the split to the rise time of the signal? I've heard that the propagation delay of the split should be no more than 1/5 of the rise time of the signal in order for the mismatch to not affect the signal. Is this accurate? Is there a better rule of thumb that considers the amount of the mismatch itself? Thanks, Jacob Foor Hewlett Packard Houston, TX Jacob.Foor@xxxxxx ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu