[SI-LIST] Differential Impedance Mismatch Rule of Thumb

Suppose there is a differential pair highly coupled with 100 diff.
impedance routed on a PCB.  Suppose there is an obstacle in the way such
that the pair must be split for time, thus incurring an impedance
mismatch.  Is there a general rule of thumb for acceptable impedance
mismatch that correlates the propagation delay of the split to the rise
time of the signal?  I've heard that the propagation delay of the split
should be no more than 1/5 of the rise time of the signal in order for
the mismatch to not affect the signal.  Is this accurate?  Is there a
better rule of thumb that considers the amount of the mismatch itself?
 
Thanks, 
 
Jacob Foor
Hewlett Packard
Houston, TX
Jacob.Foor@xxxxxx

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