[SI-LIST] Re: Differential Impedance Mismatch Rule of Thumb

Hi Jacob,

I guess it depends on how much reflection your
system could accept before noise margins reduce
to a point where your system is at risk of seeing errors.

Taking an alternate look at the problem one approach sometimes
used in backplanes is to design the line impedance slightly
high to offset the lumped effect of the vias and pressfits.

You could look attacking by applying opposite approach and increase the
line width appropriately for the duration of the split whilst you route 
around the
obstacle, at least this way you could keep the odd mode impedance matched.

I don't know if anyone has tried this in other applications or if there
are any specific pitfalls in this approach, I would be interested to
hear if anyone has tried doing this and whether it proved successful.



Kind regards
Martyn Gaudion
www.polarinstruments.com
P.S. Certainly some of the test probes we develop to launch high speed
differential TDR pulses into test coupons use techniques such as cutting back
the ground planes near the test pin connection on impedance controlled test
probes - so we can maintain as constant an impedance as possible at the
launch into to the controlled impedance line under test. This has proved
successful in maintaining pulse integrity in our particular application...



At 16:23 19/12/2002 -0600, you wrote:
>Suppose there is a differential pair highly coupled with 100 diff.
>impedance routed on a PCB.  Suppose there is an obstacle in the way such
>that the pair must be split for time, thus incurring an impedance
>mismatch.  Is there a general rule of thumb for acceptable impedance
>mismatch that correlates the propagation delay of the split to the rise
>time of the signal?  I've heard that the propagation delay of the split
>should be no more than 1/5 of the rise time of the signal in order for
>the mismatch to not affect the signal.  Is this accurate?  Is there a
>better rule of thumb that considers the amount of the mismatch itself?
>
>Thanks,
>
>Jacob Foor
>Hewlett Packard
>Houston, TX
>Jacob.Foor@xxxxxx
>
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