[SI-LIST] Re: Diff.Pairs

  • From: Mike Brown <bmgman@xxxxxxxxxx>
  • To: scott@xxxxxxxxxxxxx
  • Date: Sat, 11 Oct 2003 17:27:57 -0500

Scott McMorrow wrote:

>All,
>I'd like to be very clear about several things regarding differential 
>routing:
>
>  
>
<snipped good advice and observations>

>6a) The noise environment for a differential trace that is routed on two 
>different layers as single ended nets is significantly different.  Each 
>reference plane pair will have a different noise profile that will be 
>independently injected into each single ended trace.  The difference 
>between the two is common mode noise that flows on the composite pair.
>

Scott,
how did the difference  between the noise voltages get to be common 
mode?  Given identical noise voltages on both traces, the difference is 
zero - and that is differential noise.  The CM noise is the average of 
the two noise voltages (sum/2)

>  
>If these traces are always referenced to the same plane everywhere, then 
>there will be minimal common mode radiation.  (There will however be 
>some common mode radiation as there has to be for any conductor spaced 
>from a reference plane.)  But, if there is a break in the return path at 
>any point, or a serious discontinuity, there will be a large injection 
>of common mode current into this region.  Do not be deceived.  A 
>differential pair signal that travels through differential Vias causes 
>very minor disruptions to the fields in a power/ground plane pair.  BUT 
>if you decouple them, and route them as single ended traces in totally 
>different areas of a board, you will see significant power injections 
>into the planes.  Multigigabit energy will end up on all of your power 
>and ground supplies and have the opportunity to radiate everywhere. 
>
Quite correct.

> 
>That is why we transition differential pairs through vias that are 
>closely spaced, so that the energy they inject cancels and does not 
>spread through the planes.  If we do not do this, then the noise they 
>inject does not cancel.  Lee misses this point big time.  It is a total 
>bear to design a high frequency via transition for a single ended via, 
>without loosing a substantial amount of the signal to the planes in the 
>multiple GHz region.  A differential transition is much easier.
>
>7a) Most people agree that a closely spaced differential pair will cross 
>a plane split with relative ease and that it is a bad thing to have a 
>single ended trace cross a plane split.  But, think of the the 
>differential pair that crosses plane splits all day in every PCB when 
>the signal flows through vias.  
>
Good analogy.

>As we move the vias further and further 
>apart, more and more energy will be released into the planes, until soon 
>we are transitioning two uncorrelated single ended signals.  Now, a slow 
>speed single ended signal switching at 400 MHz and with 200 ps rise 
>times is a big enough of a problem when it passes through a single ended 
>via.  But a high energy signal such as a 2.5, 3.125 or 10 Gbps signal 
>with an edge rate of between 70 and 25 ps, will cause all hell to break 
>loose on the planes.  There will be significant rise time degradation of 
>the signal as it passes through a single ended via.  To demonstrate, I 
>have placed a presentation on single ended vias that was based upon 
>simulations I've done in the frequency domain with CST Microwave on the 
>Teraspeed website.  You  can find it a http://www.teraspeed.com and then 
>follow the links to the presentations.  You'll find that if there is not 
>a ground (or a complementary differential pair via) close to a single 
>ended via transition through a 0.063" board, you will lose a large 
>amount of that signal in the inter-plane region. This manifests itself 
>as high frequency noise on the planes and additional EMI.
>
>For vias spaced larger than 150 mils away from a ground via (most signal 
>vias), there is about -0.8 dB insertion loss at 3 GHz.  This is 
>comparable to a an 8.8% reduction in the signal amplitude of a 100 ps 
>edge.  At 7 GHz (50 ps rise time) there is a -1.5 dB loss (16% amplitude 
>reduction.)  
>

Hey!  I'll take those negative losses any day.  I think it's "1.5 db 
loss" or -1.5 db gain.  To pick nits.

>These may or may not be significant losses in a design, but 
>are extremely significant to the noise and EMI profile of a board, since 
>all of this energy is being injected into the planes where it is not 
>well contained.  The implication for 2.5, 3.125 and 10 Gbps PCB designs 
>is profound.  Decouple the differential vias and get ready for increased 
>losses, increased noise and increased EMI.
>
>
>Best regards,
>
>scott
>
>  
>
I've been laying low on this thread, but I might as well weigh in on the 
coupling issue.

If the pair is loosely coupled, or uncoupled, it is possible to 
introduce noise onto one line and not the other.  This is differential 
noise and that's most undesirable.  The receiver does little to reject 
differential noise.  At signal transitions, it has no DM rejection 
capability.  Any rejection is a function of the differential signal 
levels, not the receiver.

If the pair is closely coupled, at least a portion of the noise injected 
onto one line is coupled onto the complement line.  This is a conversion 
of differential noise into common-mode noise, and that's good.  The 
receiver is ostensibly designed to reject CM noise.  Many are quite good 
at it.

If there are no noise sources; coupling doesn't make much difference, 
nor does CM termination.
 
As to return plane current cancellation; the only way that's going to 
happen is if both traces are referenced to the same side of the same 
plane(s).  To route a differential signal in different layers, with 
different reference planes, is to throw away any noise rejection 
advantage provided by differential signalling.  You have two single 
ended signals, two different image current return paths, and quite 
probably two different prop delays from the driver to the receiver.  You 
can have all of that you want; you can surely have my share.

That a system routed that way works can only be testimony to the 
conservative nature of  the device specs and/or the system timing 
margins.   It would be a last resort exercise in anything I design.

Regards

Mike


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages 
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: