[SI-LIST] Re: DDR2 to Virtex 5 heating up and a few other questions
- From: steve weir <weirsi@xxxxxxxxxx>
- To: charlene radtke <chuckiesanchez@xxxxxxxxx>
- Date: Sun, 31 Jan 2010 12:56:20 -0800
Charlene, there are already some good responses. My question to you is
where are you with respect to your power demand and thermal analysis?
If you have not done them yet, late is better than never.
Just a summary list of things that can impact your consumption, some
already mentioned:
Driver selection: DCI enabled will greatly increase consumption over
disabled. SSTLxx Type 2 w/ DCI is particularly power hungry. The
removed series resistors will aggravate the difference between the two
designs.
LDO selection: 2 quadrant operation is required for Vtt. If your LDO is
single quadrant, then the terminators in the FPGA will dissipate more
depending on data pattern.
Timing. If you have gross errors you could be seeing momentary cross
conduction at bus turnaround when going from memory write to read
operations.
Steve.
charlene radtke wrote:
> Hello Experts,
> I have a Virtex 5 FPGA connected to a Micron DDR2 device running at 180MHz. I
> designed a prototype and am now spinning the design for another phase of my
> program. Both designs use the same V5 and the only difference between the
> DDR2s used in each design is that one if a -3 and the other is a -3E version.
>
>
> These are the differences in the 2 design:
> The Layout had some improper return paths set up for Vref and Vtt that
> were corrected in the 2nd design.
> I had series resistors on all data lines in the prototype that were
> removed in the 2nd design.
> I used all STTL18 class 1 on all IO in prototype. In the 2nd design I
> experimented with STTL18 class 1 and class 2 on control and data lines. (I
> read several app notes that mentioned both - and am currently confused on
> what is the correct approach)
> On both designs, data transfer stops working beyond 180MHz.
> On the prototype design, I didn't notice the heat that I am noticing on
> the 2nd design.
>
> During my DDR2 tests, current consumption spikes up to 2.12A from approx
> 1.2A as read from the power supplies.
> I am using a TI switch regulator to produce 1.8V.
> I am using a 0.9v LDO for VTT VREF that is enabled by a seperate FPGA on
> the board (not the V5).
>
> According to the system monitor in the V5, the temperature peaks at about 66
> deg C on the 2nd design (about 10 deg hotter than the prototype design). I'm
> not sure if this is an issue with the DDR2 or the V5 but I really want to
> understand what could be causing this. I have checked bus contention and have
> also tried running DDR2 with various IO standards.
>
> Any brainstorming assistance and advice is appreciated.
> Charlene
>
>
>
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--
Steve Weir
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