[SI-LIST] Re: DDR2 to Virtex 5 heating up and a few other questions
- From: Hany Fahmy <hfahmy@xxxxxxxxxx>
- To: "'weirsi@xxxxxxxxxx'" <weirsi@xxxxxxxxxx>, "'chuckiesanchez@xxxxxxxxx'" <chuckiesanchez@xxxxxxxxx>
- Date: Sun, 31 Jan 2010 14:24:26 -0800
My 2-cents:
1-from memory-schmoo data, u find out which byte lane is the worst and wether
it is read or write marginality.
2- pls look @ the eye-diagrams of bits within the worst-byte lane: assuming the
schmoo-data is saying that data bus is the marginal one.
3-based on # 1 and 2: try to root-cause the marginality in the eye-diagram by
extracting the layout for the DQ signal u probed with a tool such as Momentum
or HFSS to get the S-parameters: it is highly recommended to extract the whole
byte lane: all eight DQ signals and then also DQS. I personally recommend
Momentum as it is accurate and fast in getting S-parameters with models for
impedance, X-talk, return-path discontinuity if signals are making transistion
along with stitching and proximity of the stitching.
4-after getting S-parameter model, u can correlate the model with TDR
simulations vs TDR measurements of the bare-PCB.
5-run first PRBS linear driver model to find-out the marginality is coming from
the layout (passive interconnects) or it is coming from the drivers and/or
receivers.
6-get accurate models of the drivers/receivers, highly recommend encrypted
transistor models from Micron and also from Virtex. Then run eye-diagram
simulations and try to correlate with eye-diagram measurements.
6-from 4 and 5 above, u will find out whether it is a layout problem, or
driver/receiver or settings of the driver Ron/SR or termination ODT, or is it
the SSO noise on the brd, or is it the Vref signal, u may want also to measure
the Vref signal and see the amount of noise on it and also extract it on the
brd using Momentum and run the bye lane and see how much sso noise is coupled
to Vref.
Above methodology depends on the handshaking between lab and simulations to
root-cause the problem, then optimize a solution space.
Parameters to optimize:
1-width/spacing of the DQ signals. Which impact the impedance and X-talk.
2-layers of routing and transitions along with stitching and proximity of
stitching.
3- driver and receiver Ron, ODT, SR optimization.
4-vref signal routing optimization or the optimization of the set-point of
Vref.
Hany Fahmy
4-
----- Original Message -----
From: si-list-bounce@xxxxxxxxxxxxx <si-list-bounce@xxxxxxxxxxxxx>
To: charlene radtke <chuckiesanchez@xxxxxxxxx>
Cc: si-list@xxxxxxxxxxxxx <si-list@xxxxxxxxxxxxx>
Sent: Sun Jan 31 12:56:20 2010
Subject: [SI-LIST] Re: DDR2 to Virtex 5 heating up and a few other questions
Charlene, there are already some good responses. My question to you is
where are you with respect to your power demand and thermal analysis?
If you have not done them yet, late is better than never.
Just a summary list of things that can impact your consumption, some
already mentioned:
Driver selection: DCI enabled will greatly increase consumption over
disabled. SSTLxx Type 2 w/ DCI is particularly power hungry. The
removed series resistors will aggravate the difference between the two
designs.
LDO selection: 2 quadrant operation is required for Vtt. If your LDO is
single quadrant, then the terminators in the FPGA will dissipate more
depending on data pattern.
Timing. If you have gross errors you could be seeing momentary cross
conduction at bus turnaround when going from memory write to read
operations.
Steve.
charlene radtke wrote:
> Hello Experts,
> I have a Virtex 5 FPGA connected to a Micron DDR2 device running at 180MHz. I
> designed a prototype and am now spinning the design for another phase of my
> program. Both designs use the same V5 and the only difference between the
> DDR2s used in each design is that one if a -3 and the other is a -3E version.
>
>
> These are the differences in the 2 design:
> The Layout had some improper return paths set up for Vref and Vtt that
> were corrected in the 2nd design.
> I had series resistors on all data lines in the prototype that were
> removed in the 2nd design.
> I used all STTL18 class 1 on all IO in prototype. In the 2nd design I
> experimented with STTL18 class 1 and class 2 on control and data lines. (I
> read several app notes that mentioned both - and am currently confused on
> what is the correct approach)
> On both designs, data transfer stops working beyond 180MHz.
> On the prototype design, I didn't notice the heat that I am noticing on
> the 2nd design.
>
> During my DDR2 tests, current consumption spikes up to 2.12A from approx
> 1.2A as read from the power supplies.
> I am using a TI switch regulator to produce 1.8V.
> I am using a 0.9v LDO for VTT VREF that is enabled by a seperate FPGA on
> the board (not the V5).
>
> According to the system monitor in the V5, the temperature peaks at about 66
> deg C on the 2nd design (about 10 deg hotter than the prototype design). I'm
> not sure if this is an issue with the DDR2 or the V5 but I really want to
> understand what could be causing this. I have checked bus contention and have
> also tried running DDR2 with various IO standards.
>
> Any brainstorming assistance and advice is appreciated.
> Charlene
>
>
>
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--
Steve Weir
IPBLOX, LLC
150 N. Center St. #211
Reno, NV 89501
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