[SI-LIST] Re: DDR2 Clock and DQS Lines
- From: "Kai Keskinen" <kalevi@xxxxxxxxxx>
- To: <kenny_frohlich@xxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Sat, 30 Dec 2006 20:42:14 -0500
Kenny:
Read any app note from anyone that makes a DDR or DDR2 controller. Your AMD
app note is telling you the right way to implement your interface if you
want it to work. The strobe has to have some tolerance to the clock and then
the data bits corresponding to that strobe have to have even tighter
tolerance to the strobe. This forms a byte lane. You can also check out the
DDR or DDR2 JEDEC specs at the JEDEC site for more details. Micron has a
wealth of application notes too.
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Kenny Frohlich
Sent: Tuesday, December 26, 2006 10:57 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 Clock and DQS Lines
Hi All,
I understand that DQ and DQM lines need to match length with DQS lines,
and Addr/Control lines need to length match with clocks. But do DQS lines
need to length match with clocks?
In AMD design guidelines, they specifies that DQS lines need to length
match with DDR2 clocks. But is this really a requirement (industry
standard)?
Thanks,
Kenny
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