[SI-LIST] Re: DDR2 Clock and DQS Lines
- From: <Cortex.Chen@xxxxxxxxxxxx>
- To: <kenny_frohlich@xxxxxxxxx>
- Date: Wed, 27 Dec 2006 12:18:06 +0800
Kenny,
Yes.=20
Regards,
Cortex
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Kenny Frohlich
Sent: Wednesday, December 27, 2006 11:57 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] DDR2 Clock and DQS Lines
Hi All,
I understand that DQ and DQM lines need to match length with DQS =
lines, and Addr/Control lines need to length match with clocks. But do =
DQS lines need to length match with clocks?
In AMD design guidelines, they specifies that DQS lines need to length =
match with DDR2 clocks. But is this really a requirement (industry =
standard)?
=20
Thanks,
Kenny
=20
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