Hi All, I'm doing some timing analysis on the DDR2 interface and am in need of some information. The JEDEC standard and device specs will eventually be moving to 667 and 800 MBPS, however most of the timng requirements are still listed as tbd. If anyone can fill in the blanks for me at these frequencies that would be very helpful. I need set up and hold requirements for DQ to DQS and also for Address to Clock. Also need DQ and DQS output skew on the read and DQ to DQS hold. Thanks! John Ellis Vice President Interconnect Technology TriCN, Inc. 3605 Vartan Way Suite 301 Harrisburg, PA 17110 Phone:717-657-1002 Fax: 717-221-1185 email:jellis@xxxxxxxxx www.tricn.com This email message is for the sole use of the intended recipient(s) and may contain confidential and privileged information. Any unauthorized review, use, disclosure or distribution is prohibited. If you are not the intended recipient, please contact the sender by reply email and destroy all copies of the original message. ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu