[SI-LIST] DDR2- 800MBPS timing requirements

  • From: "John Ellis" <jellis@xxxxxxxxx>
  • To: <si-list@xxxxxxxxxxxxx>
  • Date: Fri, 10 Oct 2003 09:39:22 -0400

Hi All,

I'm doing some timing analysis on the DDR2 interface and am in need of some
information.
The JEDEC standard and device specs will eventually be moving to 667 and 800
MBPS, however most of the timng requirements are still listed as tbd.

If anyone can fill in the blanks for me at these frequencies that would be
very helpful.

I need set up and hold requirements for DQ to DQS  and also for Address to
Clock.

Also need DQ and DQS output skew on the read and DQ to DQS hold.

Thanks!

John Ellis

Vice President
Interconnect Technology

TriCN, Inc.

3605 Vartan Way
Suite 301
Harrisburg, PA  17110

Phone:717-657-1002
Fax:  717-221-1185
email:jellis@xxxxxxxxx

www.tricn.com

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