[SI-LIST] Re: Clock jitter
- From: Vinu Arumugham <vinu@xxxxxxxxx>
- To: k.kanakaraj@xxxxxxxxxxxxx
- Date: Mon, 19 Sep 2005 09:18:26 -0700
Definition of the various types of jitter can vary. This is a good
starting point:
http://www.jedec.org/download/search/jesd65b.pdf
Thanks,
Vinu
rajneesh.raveendran@xxxxxxxxx wrote:
>Hello,
>
>Please check out the following url from Cypress Semiconductors.
>
>http://www.cypress.com/portal/server.pt?space=3DCommunityPage&control=
>=3DSetC
>ommunity&CommunityID=3D209&PageID=3D418&r_folder=
>=3DApplication%20Notes&r_title
>=3DPerfect%20Timing%20Book
>
>Hope this helps.
>
>Regards,
>Rajneesh
>
>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Kanakaraj
>Sent: Monday, September 19, 2005 8:19 PM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Clock jitter
>
>
>-- Attached file included as plaintext by Ecartis --
>
>Hi All,
>
>Can anyone explain about clock jitter and the parameters associated with
>it?
>
>I find many parameters like=0D
>1) Deterministic Jitter
>2) Random jitter
>3) RMS jitter
>4) Peak to peak jitter
>5) Accumulated jitter.
>6) Phase jitter
>
>or is there any literature available for the same?
>
>Thanks
>~Kanak
>
>
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