[SI-LIST] Re: [Bulk] Low ESL capacitor footprints
- From: Ray Anderson <reanderson@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Thu, 09 Sep 2004 09:12:40 -0700
Dr. Edward P. Sayre wrote:
>Folks:
>
>I have a need for in-depth information regarding buildable footprints for
>Inter-digitated bypass capacitors (IDCs) in the 0805 size. I am reluctant
>to recommend multiple via hits in the pad since I have questions whether it
>is worth the hassle.
>
>I also need to find out what is any inductance inductance effects can be
>expected when there are thermal vias at the connection points in the
>power/ground planes rather than a standard via.
>
>An equivalent circuit would be helpful with different element values for
>different pad/via configurations questioned above.
>
>Thanks -
>
>ed sayre
>
>
Ed-
I'll let others comment on the IDC issue. Regarding the inductance of
the thermal vias, a couple points:
* You should be able to estimate the contribution to the via inductance
of the thermal ties by first determining the unrelieved spreading
inductance for your stackup and then scaling that value by the fraction
of the copper to open space in your vias thermal ties. You could count
rectilinear squares of copper for a more precise answer.
* In most cases thermal vias are used to aid in the solderability of
leaded components connected to a plane. I would think the inductance of
the leaded components would just about bury the additional inductance
contributed by the thermally escaped vias in the noise.
Try doing a search on the list archives using "thermal vias" for further
relevant discussion from the past.
-Ray
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