[SI-LIST] Re: [Bulk] A question about clock EMC
- From: "Kirby Goulet" <kgoulet@xxxxxxxx>
- To: <jasonleehan@xxxxxxxxx>
- Date: Wed, 2 Jan 2008 07:03:40 -0500
Han,
As you did not mention how long the line is, one thing to watch that the
combination of line length, capacitance, and series termination do not cause
a change in the DC level: a complete low or high transition may not be
possible and this reduces the voltage margin. I noticed this last month on
someone's board where the series termination allowed a 1.3V initial
transition, but the signal average value was 2V. This was a very long line
for 100MHz, but adding a capacitor could have a similar effect.
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