[SI-LIST] A question about clock EMC

  • From: "Han Li" <jasonleehan@xxxxxxxxx>
  • To: "SI LIST" <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 2 Jan 2008 09:48:53 +0800

Hi, experts.
      I am doing a board design, on which I have a 66MHz (3.3V), and a
25MHz(3.3) oscillator. I used seriese termination for these clock lines.
topoloy like this
[A]--[seriesRes]----------long line-------------[Load]
[A] is clock source,  then resistor , then transmission line ,then load at
end.
But our EMC consultant recommended me to add a cap between series Resi and
GND. The cap and resistor  are located very close. so topoloy now like this:
[A]----[seriesRes]----------long line-------------[Load]
                            |
                          ----
                          ----  ( capacitor)
                            |
                         GND
He didnot recommentd cap's value, only  said it  may help EMC  test.
I understand that such a cap can increase clock rising time and reduce
frequency spectra. BUT, donnot we creat a matched transmission line using
series resistor? Why intentionally add a cap to destroy such a matched line?
Can I really get a good EMC result?
Could anyone provide a deeped and more detailed explanation on this?
Thank  you very much.

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                //www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

Other related posts: