[SI-LIST] Re: Any basic idea about on-chip clock skew detection?

  • From: steve weir <weirsp@xxxxxxxxxx>
  • To: cyr_1976@xxxxxxxxx, si-list@xxxxxxxxxxxxx
  • Date: Mon, 18 Oct 2004 10:26:41 -0700

Yiran, there are methods to statistically grade the skew, but I don't know 
how useful that would actually be to you.  Essentially, you build a local 
delay line(s) from logic and run a metastable event capture / counter 
circuit(s).  The problem is one of calibrating the unit delays without 
gobbling up lots and lots of logic, and/or eating up a DLL or PLL.  For 
circuit details, just search "metastable" in Google.

Maybe someone else knows of a way to get around the driver delays and 
packaging effects, but if you go off-chip by conventional means, the skew 
you measure will be buried by other effects.

Assuming that your foundry has characterized their process well, I think 
you will get the most accurate results for process corners from your tools.

Steve.


At 03:29 PM 10/18/2004 +0000, Yiran Chen wrote:

>Hi, guys
>
>Do you know how to measure two clock signal's skew by using some on-
>chip method? Such as circuit and so on? If not, how could we do it
>offchip? need two pin and two same-length wires or...?
>
>Many thanks.
>
>Yiran
>
>
>
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