[SI-LIST] AW: Re: Flooded Vias vs Thermal Relief
- From: "Havermann, Gert" <Gert.Havermann@xxxxxxxxxxx>
- To: "Jack Olson" <pcbjack@xxxxxxxxx>, wjcsongr@xxxxxxxxxxxxxxxxxxx
- Date: Fri, 19 Mar 2010 16:36:20 +0100
Jack,
besides the common problems with having or not having thermal spokes, I had
signal integrity issues caused by spokes once. Problem was, that some spokes
were removed by the EDA software because there was not enough space. There were
not enough spokes, wich forced the return current to take a detour, wich rose
the inductance at that part significantly.
But you shouldn't worry for your field of work, bekause my design was a 20GHz
SMA launch on a Testfixture, and those launch designs are typically very picky
about even very small changes.
In the redesign I still used spokes, but I double checked that they were not
removed at the positions I absolutely needed them.
Unless you are pushing the envelope to very high frequencies (>>10GHz), don't
worry too much about SI-problems caused by thermal spokes.
BR
Gert
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-----Ursprüngliche Nachricht-----
Von: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] Im
Auftrag von Jack Olson
Gesendet: Freitag, 19. März 2010 15:39
An: wjcsongr@xxxxxxxxxxxxxxxxxxx
Cc: SI-LIST
Betreff: [SI-LIST] Re: Flooded Vias vs Thermal Relief
I don't have any problem doing it either way.
I was just wondering if there were ever signal integrity problems with spokes
Glad I could provide you with a laugh
(The thought of firing someone for doing something in the absence of any
instruction either way gave ME a good laugh, in a SAD kinda way. Glad I don't
work for IBM!)
Jack
.
On Fri, Mar 19, 2010 at 9:33 AM, <wjcsongr@xxxxxxxxxxxxxxxxxxx> wrote:
>
> Steve,
>
> My back of the envelope reasoning is, if you don't need them, don't
> put them in...regardless of electrical properties.
>
> Jack, you say you used thermal reliefs 'because they are easier to see'?
> Huh? What kind of tool are you using?
>
> Jerry Bartley, one if not THE big SI dog at IBM, a man who I worked
> with extensively, and has more knowledge on this stuff than most of us
> put together, would have you fired for adding thermals so you could
> see the via pads! Seriously...(LOL!)
>
> Regards,
>
> Bill
>
> William Csongradi
> Senior Electrical Engineer
> Rockwell Collins Heads Down Display Center
> 319-295-7884
>
> Mailing Address
> Rockwell Collins
> 400 Collins Road NE
> MS 105-167
> Cedar Rapids, Iowa 52498-0001
>
>
>
>
> *steve weir <weirsi@xxxxxxxxxx>*
> Sent by: si-list-bounce@xxxxxxxxxxxxx
>
> 03/19/2010 09:14 AM
> To
> Jack Olson <pcbjack@xxxxxxxxx>
> cc
> SI-LIST <si-list@xxxxxxxxxxxxx>
> Subject
> [SI-LIST] Re: Flooded Vias vs Thermal Relief
>
>
>
>
> Jack, I would demand that anyone promoting such an idea back it up
> with real numbers. The back of my envelope shows that for reasonable
> thermal ties the difference between solid and tied is about 24pH for a
> via pair, or the equivalent of less than 2mils Z axis.
>
> Steve.
>
> Jack Olson wrote:
> > Greetings,
> > I am being instructed to flood all vias instead of using thermal
> > relief,
> to
> > get a "better" connection to planes. I've typically used thermal
> > reliefs simply because they are easier to see in checking or design
> > reviews (but
> its
> > only one mouse click for me to change them so I'm not really
> complaining).
> >
> > but it got me thinking.....
> >
> > Have any test results ever showed that spokes have a significant
> impedance
> > or anything that can change circuit performance?
> > (and I'm referring to 12mil plated through-hole vias on boards
> > 100MHz
> max)
> >
> > I don't remember anyone ever talking about that.
> >
> > surfin' the learnin' curve,
> > Jack
> >
> >
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>
>
> --
> Steve Weir
> IPBLOX, LLC
> 150 N. Center St. #211
> Reno, NV 89501
> www.ipblox.com
>
> (775) 299-4236 Business
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