[SI-LIST] Re: AC Coupling for SERDES Links across Backplane
- From: "Rotem Gazit" <rotemg@xxxxxxxxxxxx>
- To: <harjeet.randhawa@xxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Thu, 28 Oct 2004 10:07:23 +0200
Hi Harjeet,
AC coupling on XAUI lines is indeed part of the 802.3ae requirements.
This gives the IC vendors freedom to design using different common mode
voltage without creating interoperability problem.
If you use the same vendor XAUI SerDes in both sides of the link
omitting the capacitors MAY work (receiver and transmitter within the
same chip may still have different common mode).
This information should appear in the datasheet of the part you are
using.
Regards,
________________________________________
Rotem Gazit
Director System & Product Engineering.
Mysticom Semiconductor Ltd.
Tel: +972 9 8636424
Fax: +972 9 8636466
1 Hazoran St, Netanya 42504, Israel.
www.mysticom.com
=20
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Harjeet Randhawa
Sent: Thursday, October 28, 2004 9:04 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] AC Coupling for SERDES Links across Backplane
Hi All,
The XAUI spec mandates putting the AC coupling CAPs for the SERDES links
to allow inter-operability among different SERDES technology vendors due
to probable different internal BIAS levels.
But for the scenarios where the SREDES cells are same does it helps in
any way to AC Couple the SERDES links. The scenarios may be where there
is 40" of PCB trace running from a line card to backplane and finally to
a Fabric Card.
The SERDES cells are matched in the sense that they are having same
characteristics and from same vendor. The BIAS voltage is generated on
board with 5% regulation. I do not expect any high current transients on
the BIAS voltage and it is well filtered and decoupled.
Also there is a consistent Ground Plane bridging at backplane connectors
so the GND differential across the TX to RX points should not cause any
significant BIAS reference shifts.
The whole issue is due to fact that the Transmit Pairs of the SERDES are
2-3 rows deep in the package so adding the AC Cap will force to add two
more VIAs on the routes adding to deterioration of the signaling
quality.
Thanking all in advance for their valuable suggestions.
Best Regards,
/---------------------------------------------------------/
Harjeet S Randhawa,
Nevis Networks INC.
/--------------------------------------------------------/
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