[SI-LIST] Re: A question about clock EMC
- From: steve weir <weirsi@xxxxxxxxxx>
- To: jasonleehan@xxxxxxxxx
- Date: Tue, 01 Jan 2008 18:52:17 -0800
Han, if you have an emissions problem from the clock line that lies
above the clock frequency, then the clock signal rise-time could be an
issue. Your consultant is suggesting that you slow down the rise-time.
I don't know the particulars of your system, but I would be inclined to
try and keep the line from radiating first, and attack the rise-time
only if that is not feasible.
If you do want to slow down the rise time, an R-C-R network would be a
better choice than an R-C. The R-C largely defeats the reflected
termination function of the termination resistor. This could cause
unwanted signal integrity problems with the clock. An R-C-R network,
the second R is close to the desired termination resistance, and the
first R is substantially smaller, typically 1/5th.
The RC time constant that you are after is one that:
* Is significantly smaller than the bit interval. Otherwise you
introduce substantial timing distortion.
* Is significantly longer than the rise-time of the oscillator w/o the
network.
But honestly, it sounds like your consultant is asking you to apply a
band-aid before it is clear that you even have a problem. Unless you do
something unfortunate like provide a poor return path, or have a nasty
package resonance, a single clock line should not be a problem.
Steve.
Han Li wrote:
> Hi, experts.
> I am doing a board design, on which I have a 66MHz (3.3V), and a
> 25MHz(3.3) oscillator. I used seriese termination for these clock lines.
> topoloy like this
> [A]--[seriesRes]----------long line-------------[Load]
> [A] is clock source, then resistor , then transmission line ,then load at
> end.
> But our EMC consultant recommended me to add a cap between series Resi and
> GND. The cap and resistor are located very close. so topoloy now like this:
> [A]----[seriesRes]----------long line-------------[Load]
> |
> ----
> ---- ( capacitor)
> |
> GND
> He didnot recommentd cap's value, only said it may help EMC test.
> I understand that such a cap can increase clock rising time and reduce
> frequency spectra. BUT, donnot we creat a matched transmission line using
> series resistor? Why intentionally add a cap to destroy such a matched line?
> Can I really get a good EMC result?
> Could anyone provide a deeped and more detailed explanation on this?
> Thank you very much.
>
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