[SI-LIST] Re: 50 Ohm Via?
- From: wolfgang.maichen@xxxxxxxxxxxx
- To: joel@xxxxxxxxxx
- Date: Wed, 9 Jan 2008 19:00:05 -0800
Joel,
depends very much on your specific board layout (and the degrees of
freedon you have inchoosing layers, dimensions etc.). Sometimes there are
simple solutions that give reasonable performance.
Best (easiest) case would be if your routing density is not too high, and
the transition goes from a layer at or at least close to the top surface
to a layer at or close to the bottom surface of your board, so the
resulting stubs are very short and can be neglected in first order (i.e.
most of or all of the via is part of the intended signal path). Of course
if there are significant stubs you could still do backdrilling to remove
them. Then you could add several vias (4 is a good number that still
allows for trace escape from the central signal via) for the return
current (i.e. stitching the reference planes together) around that signal
via in a quasi-coaxial configuration (i.e. on the four corners of a square
centered at the signal via). Next step is to clear all planes in the area
between those return vias (and maybe even slightly beyond, except below
the signal trace leading to the via). You can now use a simple 2D field
solver or even some closed formulas to adjust the distance between signal
and return via, and also the via diameter, to obtain 50 Ohm impedance.
Obviously that will only give an approximation to a true 50 Ohm structure
- it neglects stubs (if the signal traces are not at the surface),
fringing fields at the ends of the via, the effect of the other planes
(you can't cut out too far), the annular rings of the via (will add
capacitance), and finally the trace section close to the via will be
inductive (because there is no ground plane). But I recently consulted on
such a "quick and dirty" design and at first pass achieved a bandwidth of
over 20 GHz through the via, and the structure itself came out to 47 Ohms
(I'm not ruling out a certain amount of luck here - don't hold me
accountable if your first try doesn't work out as nicely :-) With a very
fast TDT I was also able to observe all the parasitic effect mentioned.
Also, keep in mind that even with the best 3D field solver and many months
of effort your result will only be as good as your input data. In your
model you know and control exactly every single parameter. But in practice
there are tolerances everywhere - the dielectric constant may be off by a
few percent, the traces and planes have etching tolerances, the via may be
drilled slightly off-center, etc. etc. So even if your field solver
predicts 50.00000 Ohms for a given configuration, the structure in the
real board can be off by several Ohms. (and that doesn't even take into
account that you may have a mistake in your model setup). So I'd also make
a judgement call how much simulation effort / time / cost it is really
worth, as opposed to e.g. do a combined approach of simulation + some
simple test board(s) to gain confidence and experience. Once your test
boards match your simulation I'd be much more confident that my simulation
can accurately predict my real, complex design. (and in addition you'll
get a better feeling as to how precisely your simulation model can predict
different structures).
Wolfgang
"Joel Brown" <joel@xxxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
01/09/2008 05:51 PM
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joel@xxxxxxxxxx
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Subject
[SI-LIST] 50 Ohm Via?
Is there such a thing as a design methodology for designing a PCB via with
50 ohm impedance, or does it have to be done iteratively using a 3D field
solver?
Are controlled impedance vias necessary, worthwhile or helpful for
multi-gigabit serial links running at 1 to 5 Gbps?
Thanks - Joel
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