[PCB_FORUM] Re: differential spacing clearance specification prob lem...
- From: "Feehan, Stephen" <Stephen.Feehan@xxxxxxxxxxx>
- To: "'icu-pcb-forum@xxxxxxxxxxxxx'" <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 21 Mar 2005 12:02:41 -0800
Hello Austin,
If you add a Diffp_min_space property = 4.5 mil it will clear the DRC.
This is a new constraint that was added in V15.2.
-Stephen
-----Original Message-----
From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
Sent: Monday, March 21, 2005 2:23 PM
To: PCB Forum Mailing List
Subject: [PCB_FORUM] differential spacing clearance specification
problem...
Hi,
I have set-up the following in Allegro 15.2:
Using the Constraint Manager spreadsheet, differential signals are paired.
Line spacing and gap etc. are NOT specified in the spreadsheet, only phase
tolerance and uncoupled length.
In Constraints/Physical rule set I setup a Constraint Set Name "100_OHM_DE"
and have set DiffPair primary gap to 4.5 mils.
In Constraints/Spacing rule set I setup a Constraint Set Name "DIFF_SPACING"
and give a Line to Line spacing of 9 mils.
What my goal is here, is to have a differential gap of 4.5 mils, and a
differential pair to any other signal clearance of 9 mils.
I then set-up via the assignment table and constraint manager so that these
rules apply to the differential pair signals under General
Properties/Physical, using Constraint Sets-Physical & Spacing.
What I get are trace to trace DRC errors within a differential pair, saying
the target clearance is 9 mils, and there is only 4.5. There should only be
4.5, and it should not be checking trace to trace within the differential
pair. What am I doing wrong? It *works* right, in that I get a
differential gap of 4.5, and I get a pair to other signal spacing of 9, but
I get the LL DRC errors.
Regards,
Austin
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