[PCB_FORUM] Re: differential spacing clearance specification problem...
- From: "Rix, Randy B" <randy.b.rix@xxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Mon, 21 Mar 2005 12:02:00 -0800
Austin,
The Minimum Line Spacing needs to be defined in CM as the smallest gap
minus the negative tolerance (note that the smallest gap also includes
the neck gap). Probably in your case, it will be 4.5 mils. (for
example if you had a negative tolerance of 0.1 mils, you would set the
Min Line Spacing to 4.4 mils)
Sourcelink has some really good details on setting up diff pairs.
-Randy
It's my opinion, not my company's.
-----Original Message-----
From: Austin Franklin [mailto:austin@xxxxxxxxxxxx]
Sent: Monday, March 21, 2005 11:23 AM
To: PCB Forum Mailing List
Subject: [PCB_FORUM] differential spacing clearance specification
problem...
Hi,
I have set-up the following in Allegro 15.2:
Using the Constraint Manager spreadsheet, differential signals are
paired.
Line spacing and gap etc. are NOT specified in the spreadsheet, only
phase tolerance and uncoupled length.
In Constraints/Physical rule set I setup a Constraint Set Name
"100_OHM_DE"
and have set DiffPair primary gap to 4.5 mils.
In Constraints/Spacing rule set I setup a Constraint Set Name
"DIFF_SPACING"
and give a Line to Line spacing of 9 mils.
What my goal is here, is to have a differential gap of 4.5 mils, and a
differential pair to any other signal clearance of 9 mils.
I then set-up via the assignment table and constraint manager so that
these rules apply to the differential pair signals under General
Properties/Physical, using Constraint Sets-Physical & Spacing.
What I get are trace to trace DRC errors within a differential pair,
saying the target clearance is 9 mils, and there is only 4.5. There
should only be 4.5, and it should not be checking trace to trace within
the differential pair. What am I doing wrong? It *works* right, in
that I get a differential gap of 4.5, and I get a pair to other signal
spacing of 9, but I get the LL DRC errors.
Regards,
Austin
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