[PCB_FORUM] Re: Retaining nets on free-standing vias
- From: "Cosentino, Tony" <Tony.Cosentino@xxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 2 Mar 2006 12:23:23 -0600
I agree, it is a great source of pain that seems to never go away.
Release after release comes out and this problem is never addressed. I
once suggested giving users the ability to add vias (special vias -
maybe called Stitching Via) that the user can assign a net to. It would
act like a PIN but would not be required in the schematic. Cadence added
the ability to logically connect a net to a PIN but it will only add the
net to a pin from a component (not a symbol). If it would allow you to
add a net to a manually placed symbol then you could add the vias as
single pin symbols but of course it does not allow this.
We always make sure there is an external copper shape to hold our vias
net name and we manually manipulate that shape watching carefully to be
sure the intended net name is associated with the via. In some other
cases (very few) we add a connect line to each via to retain the net
name. However this causes its own problems. As another user stated using
negative planes does help simplify the problem but when you have
different shapes on either external layer then the problem can not be
simplified by negative internal planes.
Hopefully someone else has a better plan and will share this with the
group
Thanks
Tony Cosentino
Tekelec
Tony.cosentino@xxxxxxxxxxx
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of
Michael.Catrambone@xxxxxxxxxx
Sent: Thursday, March 02, 2006 12:55 PM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Retaining nets on free-standing vias
Hello,
I deal with this all the time.. The best way I found to handle it was to
define a small static shape on top of the via with the net name attached
to it. This shape is defined a little larger than the via geometry on
the top side of the PCB and whenever I move the via I make sure to
select the shape as well.
Kind of a pain but it gets me past the problem. Maybe someone else has
a better way of handling this.
Mike
"Daniel So" <danielso@xxxxxxxxxxxxx>@freelists.org on 03/02/2006
11:43:43 AM
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Subject: [PCB_FORUM] Retaining nets on free-standing vias
Hi Everyone
Please excuse me if this is an old subject.
I have thru-hole vias connected to a gnd plane on the top layer. There
is +5v plane on the bottom side of the PCB. There are no clines
connected to the vias so when ever I move the gnd plane, the vias are
now associated to the +5v plane. I now have to move the +5v plane before
moving back the gnd plane if I want to keep these vias associated to
gnd. This is really a bad problem on a multi-layer board with different
planes on different layers and when I have vias that I want to keep
associated to different nets.
Is there any way to keep the vias associated to the original nets
without connecting clines to them? Cadence did not have an answer.
Thanks for any suggestions
Daniel So
email: danielso@xxxxxxxxxxxxx
(See attached file: C.htm)
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