[PCB_FORUM] Re: How-to? [Impedance]
- From: Dave Schaefer <dave.schaefer@xxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 27 Jul 2006 16:49:54 -0500
Richard,
So what you're saying is that you have no cents in New Zealand? :)
Good point on uniformity of the 4 mil traces !!
Dave
>
> From: "richard moffat" <richard.moffat@xxxxxxxxxxxxxxxxxxx>
> Date: 2006/07/27 Thu PM 04:13:28 CDT
> To: <icu-pcb-forum@xxxxxxxxxxxxx>
> Subject: [PCB_FORUM] Re: How-to? [Impedance]
>
> Likewise - good idea to have it consistent. However, 4mils is harder to
> achieve a constant impedance. The uniformity of the trace width and the
> closer proximity to the reference plane are the two bigger problems.
>
> 5.68 down to 5 isn't that big a jump, and it will only be a short distance
> (1/2 an inch?) that has a slightly higher impedance. Personally, I'd opt for
> that.
>
> On a different note, you may have to look at a 10% tolerance for fine traces
> such as these. 5% is more commonly used for wider traces such as 34 ohm used
> in Rambus.
>
> Just my 5 cents. (We don't have 1 or 2 cent coins in New Zealand anymore.)
>
> Kind regards,
> Richard
>
>
>
> >>> Dave Schaefer <dave.schaefer@xxxxxxx> 28/07/2006 7:44 a.m. >>>
> Good idea from a tool useage standpoint, but you'll create an Impedance
> "bump" - really depends upon the design as to if this is an issue. However,
> Controlled Impedance is normally employed to prevent these "bumps".
>
> For example, a design with 5 mil traces requiring neck down to 4 mils in fine
> pitch areas results in a 20% Impedance change ... why not just design
> features and stackup to use 4 mil throughout?
>
> Just another opinion to consider ...
> Dave
> >
> > From: "Feehan, Stephen \(Com US\)" <Stephen.Feehan@xxxxxxxxxxx>
> > Date: 2006/07/27 Thu PM 02:14:10 CDT
> > To: <icu-pcb-forum@xxxxxxxxxxxxx>
> > Subject: [PCB_FORUM] Re: How-to? [Impedance]
> >
> > Hi William,
> >
> > Add an area constraint around the bga and set the width to the size you
> > need.
> >
> > Here's an example:
> > Area constraint = Net_Physical_Constraint = BGA_AREA
> > Create new Net_Physical_Constraint = 5_mil_width
> >
> > Then under the assignment table set no_type in the BGA_AREA to 5_mil_width
> > constraint.
> >
> > When you route into the bga it will automatically change to 5 mils then
> > change back
> > to 5.68 when you exit the bga area. Assuming you have the default width set
> > to 5.68 for
> > the 50 ohm nets.
> >
> > Regards,
> > Stephen Feehan
> > Siemens Network Convergence
> >
> >
> > ________________________________
> >
> > From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
> > [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of William Billereau
> > Sent: Thursday, July 27, 2006 1:19 PM
> > To: icu-pcb-forum@xxxxxxxxxxxxx
> > Subject: [PCB_FORUM] How-to? [Impedance]
> >
> >
> > Hello All.
> >
> > We are actually fighting with impedances!
> > all:all:50 ohm:5%
> >
> > Allegro routes with an autocalculated line width of 5.68mils.
> > This is not possible to route inside the BGA which has an area with minimum
> > line width set to 5 mils.
> > small lenght routed with 5mils have impedance DRCs.
> >
> > I try to route them without the area using neck mode. The neck mode off the
> > line is still 5mils. It does not switch again to 5.68mils...
> > but it is not even a solution because the neck has also DRCs.. grrrrr.
> >
> > How do you generally proceed in such cases?
> >
> > Thanks in advance!
> >
> > William.
> >
> > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
> > | Billereau William | PCB Designer |
> > | | Tel: (+4122) 76 73403 |
> > | CERN TS/DEM | william.billereau@xxxxxxx |
> > | 1211 Geneve 23 Switzerland | Société: AMEC-SPIE/Electrotech |
> > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
> >
> >
>
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