[PCB_FORUM] Re: Auto Testprep
- From: "Andrew Noonan" <andrew@xxxxxxxxxxx>
- To: <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Fri, 6 May 2005 09:24:58 -0700
Kevin,
I think what Ed has shown us is an option to replace one via type with a
test-point via type. If you use a different via under BGA's compared to
the rest of your design, this will give you the flexibility to change
test point vias based on original via type.
Although, I have to admit, I do like the idea of using a particular via
type in a physical area.
Andrew
-----Original Message-----
From: icu-pcb-forum-bounce@xxxxxxxxxxxxx
[mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] On Behalf Of Kevin McCowan
Sent: Friday, May 06, 2005 4:51 AM
To: icu-pcb-forum@xxxxxxxxxxxxx
Subject: [PCB_FORUM] Re: Auto Testprep
Well, that's nice and everything but what you've shown
doesn't show how you would put different testpoints in
different areas. Will that be part of the new testpoint
stuff or is that part of the constraints?
Or, did I miss something?
Kevin
Ed Hickey wrote:
> Additional Testprep enhancements are scheduled for 15.5. (Late July)
The
> two screen shots attached show the redesigned TP parameter form that
> includes:
>
>
>
> * Expansion of Via Replacement Selections
> o /New interface in parameter form allows multiple mappings
of
> design vias to their replacement types/
> o /Reduces Testprep execution iterations/
> o /Control mappings per design or by reading in a .csv file/
>
> / /
>
> * Probe Type Attributes
> o /New interface for assignment probe type and their
> respective center to center spacing requirements/
> o /Typical types of 100, 75 and 50 mil identified
graphically
> by figures on testprobe subclass/
> o /Probe types and spacings are user definable and
> controllable from reading in a .csv file/
>
>
>
>
>
> Ed Hickey
> Product Engineer - Allegro PCB Editor
> Cadence Design Systems
> Chelmsford, MA 01824
> 978-262-6545
>
>
>
------------------------------------------------------------------------
> *From:* icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] *On Behalf Of *Dave
Mattice
> *Sent:* Thursday, May 05, 2005 1:18 PM
> *To:* icu-pcb-forum@xxxxxxxxxxxxx
> *Subject:* [PCB_FORUM] Re: Auto Testprep
>
> Same problem here. I hope Cadence is monitoring this
> Thread of letters. This is a real pain. I test prep manually
> And massage the layout for maximum coverage. With so
> Many different BGA sizes and respective fan outs used test
> Point insertion is a mistake waiting to happen. I sure would like
> To see multiple vias for test coverage and their respective
> Test access replacements allowed.
>
>
>
> Anyone have any thoughts on this? Or has someone figured out
>
> How to do this?
>
>
>
> -----Original Message-----
> *From:* icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]*On Behalf Of *JACK
KELLY
> *Sent:* Thursday, May 05, 2005 9:00 AM
> *To:* icu-pcb-forum@xxxxxxxxxxxxx
> *Subject:* [PCB_FORUM] Re: Auto Testprep
>
>
>
> we also run into this issue on most every board, we have to run
> testprep two or thee times if we use different via padstacks.
>
> -----Original Message-----
> *From:* icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx]
> *Sent:* Thursday, May 05, 2005 10:54 AM
> *To:* icu-pcb-forum@xxxxxxxxxxxxx
> *Subject:* [PCB_FORUM] Re: Auto Testprep
>
> Hi Kumaran,
>
> We run into this issue regularly. When running testprep, create
> NO_PROBE areas under the BGAs (I'll assume NO_PROBE_BOTTOM). Run
> testprep until you are satisfied with your coverage. Then, change
> the via type to the one you want under BGA's, remove the NO_PROBE
> areas and run again (make sure that you click Incremental
addition).
>
>
>
> Andrew Noonan
>
> Sr. PCB Designer
>
> Topspin Communications
>
> (w)650-316-3398
>
> (c)650-814-3677
>
> -----Original Message-----
> *From:* icu-pcb-forum-bounce@xxxxxxxxxxxxx
> [mailto:icu-pcb-forum-bounce@xxxxxxxxxxxxx] *On Behalf Of *Kumaran
> *Sent:* Thursday, May 05, 2005 8:11 AM
> *To:* icu-pcb-forum@xxxxxxxxxxxxx
> *Subject:* [PCB_FORUM] Auto Testprep
>
> Hi All,
>
>
>
> I would like to add a particular test padstack for BGAs and
another
> test padstack for other than BGA vias automatically. Is that
> possible? I see it allows only one type of padstack & inserts
> testpoints irrespective of BGA vias & other vias.Pls clarify.
>
>
>
> Regards
> Kumaran M
>
>
>
------------------------------------------------------------------------
>
>
>
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>
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