[PCB_FORUM] Re: 16.3 Constraint Manager question (Added Images)

Hi all,
I found that you can not use the Rel Prop delay property in Concept HDL schematic. I was only entering a Matched Length Group name as a value. Which it then created a ML group in Allro CM of that name, but would over write with default settings every time I packaged. I would have to incorporate a host of syntax / variables in the value field. Not intuitive at all! So, guess I am forced to create the ML group "Manually" in Allegro CM, then manually add all nets / xnets in that group. Also losing the added benefit to see the properties in the schematic. 

This came straight from Cadence.

Mark

On 4/17/2011 4:28 AM, O Migs wrote:

Hi Mark,
Just a thought. Do you have "Create user-defined properties" selected during the netin process? This option allows the creation of property definitions from the netlist. 

Best regards,

-oscar
On Thu, Apr 14, 2011 at 3:46 AM, Mark Salberg <msalberg@xxxxxxxxxxxx <mailto:msalberg@xxxxxxxxxxxx>> wrote: 

    Here is the same as original message WITH images.

    I was wondering if anyone there has run into this one?

    After adding Prop delay property on nets in schematic (Concept),
    package to Allegro, all nets are assigned to a Matched Length
    group in CM.

    Set target, add delta / tolerance and assign pin pairs as Longest
    Pin Pair. _Everything is fine until packaging schematic changes to
    Allegro next time!_
    *After packaging*, the delta / tolerance is defaulted back to *0
    mil:5%???
    Thus causing all Prop delays to fail.
    *
    Any Ideas?
    I just finished a design using this method, but it never did this.

    P.S. I really like the idea of assigning in the schematic.

    Thanks in advance,
    Mark

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