[PCB_FORUM] 16.3 Constraint Manager question
- From: Mark Salberg <msalberg@xxxxxxxxxxxx>
- To: Cadence User Group <icu-pcb-forum@xxxxxxxxxxxxx>
- Date: Thu, 14 Apr 2011 06:28:51 -0400
After adding Prop delay property on nets in schematic (Concept), package
to Allegro, all nets are assigned to a Matched Length group in CM.
Set target, add delta / tolerance and assign pin pairs as Longest Pin
Pair. _Everything is fine until packaging schematic changes to Allegro
next time!_
After packaging, the delta / tolerance is defaulted back to *0 mil:5%???
Thus causing all Prop delays to fail.
*
Any Ideas?
Anyone using this?
I just finished a design using this method, but it never did this.
P.S. I really like the idea of assigning in the schematic.
Thanks in advance,
Mark
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