[ibis-macro] Macro Model Library Release Notice

From: "Muranyi, Arpad" <arpad.muranyi@xxxxxxxxx>
To: <ibis-macro@xxxxxxxxxxxxx>
Date: Mon, 6 Feb 2006 17:08:54 -0800

Hello everyone,

I released another iteration of the IBIS macro library today.
This time both Verilog-A(MS) and VHDL-A(MS) libraries have
been updated, and they can be found in the usual place:

http://www.eda.org/pub/ibis/macromodel_wip/element_lib


The changes are as follows:

1)  I found a bug in the VHDL-A(MS) version I released last
week that caused array size mismatch errors.  I was using
the wrong vectors as input to the FndCommonLength function
in the IBIS buffer models.

2)  I also changed some of the declarations from "real" to
"current" to eliminate the warnings about using default
tolerance.

3)  As a result of getting the Perl script working, I added
three more data files to the test suite so we can simulate
with real IBIS data and get some nice rounded waveforms.
Since these waveforms are a little slower, I doubled the
simulation pulse and the length of the simulation time
for the IBIS buffer test cases so we wouldn't switch into
an unfinished edge.

4)  I also changed the algorithm of the "DIV" controlled
sources to handle the div/0 case a little more elegantly
than before.  (This was actually suggested by Maged, the
tech support guy for SMASH).  The result is that the waveforms
will be continuous (even though their derivatives are still
discontinuous), which will help to reduce convergence problems
(although it will not completely eliminate them)...


I made the same changes to the "DIV" building blocks in the
Verilog-A(MS) version of the library as well, that is the
reason for releasing that one also today.

I was not able to test the Perl script generated data with
the Verilog-A(MS) library yet due to the array parameter
resizing problems, but hopefully that will be fixed soon
too, and then we can test it also.

As usual, any comments are welcome and appreciated.

Thanks,

Arpad
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[ibis-macro] Macro Model Library Release Notice

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