[SI-LIST] Re: what level of overshoot is acceptable
- From: "Tom Dagostino" <tom@xxxxxxxxxxxxx>
- To: "'WANG Zhenwei'" <Zhenwei.Wang@xxxxxxxxxxxxxxxxxx>, <si-list@xxxxxxxxxxxxx>
- Date: Wed, 30 Nov 2011 18:51:08 -0800
Zhenwei
The max input spec is not 3.6V + 0.4V it is the present Vcc plus 0.4V. The
spec is trying to tell you not to turn on the clamp diode. The clamp diode
is referenced to Vcc and not allowing the voltage to go greater than 0.4V
above Vcc will keep the clamp diode off.
Tom Dagostino
Teraspeed Labs
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Suite 102
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USA
971-279-5325 Office
971-279-5326 FAX
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tom@xxxxxxxxxxxxx
www.teraspeed.com
Teraspeed Consulting Group LLC
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-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of WANG Zhenwei
Sent: Wednesday, November 30, 2011 6:13 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] what level of overshoot is acceptalbe
Hi guys,
I have a problem: what level of overshoot is acceptable? I was
ordered to qualify a new nand flash on my project. There are an signal
integrity measurement on overshooting. Some info form spec of nand:
1. power supply:3.3V, so the ideal logic high is 3.3V.
2. max power : 3.6V
3. Input High Voltage VIH: 2.0~ VCC +0.3; Input Low Voltage VIL,
-0.3~0.8
3. NOTE : 1) VIL can undershoot to -0.4V and VIH can overshoot to VCC + 0.4V
for durations of 20 ns or less.
So my formula is :
The max acceptable overshoot=(max power + 0.4V )/( ideal logic high
)=(3.6V + 0.4V)/3.3V!%.
Am I right?
BR
Zhenwei Wang
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- » [SI-LIST] Re: what level of overshoot is acceptable - Tom Dagostino
