[SI-LIST] Re: timing calculation Real board Vs Test load
- From: "Istvan Nagy" <buenos@xxxxxxxxxxx>
- To: <kbmanick@xxxxxxxxx>, "si-list" <si-list@xxxxxxxxxxxxx>
- Date: Thu, 5 Dec 2013 19:19:37 -0800
Hi,
I wrote about this in an article a few years ago:
http://pcdandf.com/cms/component/content/article/171-current-issue/7504-signal-integrity-
See sections called "Output guaranteed timing" and âPropagation Delayâ.
Regards,
Istvan Nagy
-----Original Message-----
From: Balamanikandan K
Sent: Wednesday, December 04, 2013 5:09 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] timing calculation Real board Vs Test load
Hi,
Timings specified in datasheet are for particular loading (eg: 10pf
loading).
When we have a real board in post layout, how can we measure the timings
using SI simulation tool? How to utilize the datasheet values for real
board measurement?
Please clarify.
--
Best Regards,
Balamanikandan.K
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