[SI-LIST] Re: thermal relief
- From: "Nagel, Michael" <Michael.Nagel@xxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Wed, 28 Apr 2004 16:40:36 +0200
Hello Jan,
> From: jan gillis [mailto:jan.gillis@xxxxxxxxxxxxxx]
> [...] For soldering purposes, it would
> be preferred to
> make use of thermal reliefs for the ground vias. But I wonder
> what would be
> the influence of the pin-to-ground plane impedance. Can
> anyone provide some
> guideline for this purpose?
I never did any simulations in this direction, but I *feel*
that a connection without thermal reliefs would be better.
This is not founded on simulation results, however.
What is the size of the vias you use? Using relatively small
vias the soldering process can easily be adopted to provide
a high yield without thermal reliefs. We had/have several boards
designed in this way.
I am also interested in simulation results ...
Best regards,
Michael
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl?Si-List_FAQ
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
